hz
This commit is contained in:
+15
@@ -0,0 +1,15 @@
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set(MCU_VARIANT MIMXRT1015)
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||||
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set(JLINK_DEVICE MIMXRT1015DAF5A)
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set(PYOCD_TARGET mimxrt1015)
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set(NXPLINK_DEVICE MIMXRT1015xxxxx:EVK-MIMXRT1015)
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function(update_board TARGET)
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target_sources(${TARGET} PUBLIC
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${CMAKE_CURRENT_FUNCTION_LIST_DIR}/evkmimxrt1015_flexspi_nor_config.c
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)
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target_compile_definitions(${TARGET} PUBLIC
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CPU_MIMXRT1015DAF5A
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CFG_EXAMPLE_VIDEO_READONLY
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)
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endfunction()
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@@ -0,0 +1,59 @@
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/*
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* The MIT License (MIT)
|
||||
*
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* Copyright (c) 2019, Ha Thach (tinyusb.org)
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*
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||||
* Permission is hereby granted, free of charge, to any person obtaining a copy
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||||
* of this software and associated documentation files (the "Software"), to deal
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||||
* in the Software without restriction, including without limitation the rights
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||||
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
* copies of the Software, and to permit persons to whom the Software is
|
||||
* furnished to do so, subject to the following conditions:
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||||
*
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||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
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||||
*
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||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
||||
* THE SOFTWARE.
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||||
*
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* This file is part of the TinyUSB stack.
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*/
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/* metadata:
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name: i.MX RT1015 Evaluation Kit
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url: https://www.nxp.com/design/design-center/development-boards-and-designs/MIMXRT1015-EVK
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*/
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#ifndef BOARD_MIMXRT1015_EVK_H_
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#define BOARD_MIMXRT1015_EVK_H_
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// required since iMXRT MCUX-SDK include this file for board size
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#define BOARD_FLASH_SIZE (0x1000000U)
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// LED
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#define LED_PINMUX IOMUXC_GPIO_SD_B1_01_GPIO3_IO21
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#define LED_PORT BOARD_INITPINS_USER_LED_PERIPHERAL
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#define LED_PIN BOARD_INITPINS_USER_LED_CHANNEL
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#define LED_STATE_ON 0
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// SW8 button
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#define BUTTON_PINMUX IOMUXC_GPIO_EMC_09_GPIO2_IO09
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#define BUTTON_PORT BOARD_INITPINS_USER_BUTTON_GPIO
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#define BUTTON_PIN BOARD_INITPINS_USER_BUTTON_GPIO_PIN
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#define BUTTON_STATE_ACTIVE 0
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// UART
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#define UART_PORT LPUART1
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#define UART_CLK_ROOT BOARD_BOOTCLOCKRUN_UART_CLK_ROOT
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#define UART_RX_PINMUX IOMUXC_GPIO_AD_B0_07_LPUART1_RX
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#define UART_TX_PINMUX IOMUXC_GPIO_AD_B0_06_LPUART1_TX
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static inline void BOARD_ConfigMPU(void) {
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}
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#endif
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@@ -0,0 +1,11 @@
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CFLAGS += -DCPU_MIMXRT1015DAF5A -DCFG_EXAMPLE_VIDEO_READONLY
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MCU_VARIANT = MIMXRT1015
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# For flash-jlink target
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JLINK_DEVICE = MIMXRT1015DAF5A
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# For flash-pyocd target
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PYOCD_TARGET = mimxrt1015
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# flash using pyocd
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flash: flash-pyocd
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+357
@@ -0,0 +1,357 @@
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/*
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* How to setup clock using clock driver functions:
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*
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* 1. Call CLOCK_InitXXXPLL() to configure corresponding PLL clock.
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*
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* 2. Call CLOCK_InitXXXpfd() to configure corresponding PLL pfd clock.
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*
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* 3. Call CLOCK_SetMux() to configure corresponding clock source for target clock out.
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*
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* 4. Call CLOCK_SetDiv() to configure corresponding clock divider for target clock out.
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*
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* 5. Call CLOCK_SetXtalFreq() to set XTAL frequency based on board settings.
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*
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*/
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/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
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!!GlobalInfo
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product: Clocks v15.0
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processor: MIMXRT1015xxxxx
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package_id: MIMXRT1015DAF5A
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mcu_data: ksdk2_0
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processor_version: 24.12.10
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board: MIMXRT1015-EVK
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* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
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#include "clock_config.h"
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#include "fsl_iomuxc.h"
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/*******************************************************************************
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* Definitions
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******************************************************************************/
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/*******************************************************************************
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* Variables
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******************************************************************************/
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/*******************************************************************************
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************************ BOARD_InitBootClocks function ************************
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******************************************************************************/
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void BOARD_InitBootClocks(void)
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{
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BOARD_BootClockRUN();
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}
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/*******************************************************************************
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********************** Configuration BOARD_BootClockRUN ***********************
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******************************************************************************/
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/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
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!!Configuration
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name: BOARD_BootClockRUN
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called_from_default_init: true
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outputs:
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- {id: AHB_CLK_ROOT.outFreq, value: 500 MHz}
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- {id: CKIL_SYNC_CLK_ROOT.outFreq, value: 32.768 kHz}
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- {id: CLK_1M.outFreq, value: 1 MHz}
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- {id: CLK_24M.outFreq, value: 24 MHz}
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- {id: ENET_500M_REF_CLK.outFreq, value: 500 MHz}
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- {id: FLEXIO1_CLK_ROOT.outFreq, value: 30 MHz}
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- {id: FLEXSPI_CLK_ROOT.outFreq, value: 2160/11 MHz}
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- {id: GPT1_ipg_clk_highfreq.outFreq, value: 62.5 MHz}
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- {id: GPT2_ipg_clk_highfreq.outFreq, value: 62.5 MHz}
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- {id: IPG_CLK_ROOT.outFreq, value: 125 MHz}
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- {id: LPI2C_CLK_ROOT.outFreq, value: 60 MHz}
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- {id: LPSPI_CLK_ROOT.outFreq, value: 105.6 MHz}
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- {id: MQS_MCLK.outFreq, value: 1080/17 MHz}
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- {id: PERCLK_CLK_ROOT.outFreq, value: 62.5 MHz}
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- {id: SAI1_CLK_ROOT.outFreq, value: 1080/17 MHz}
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- {id: SAI1_MCLK1.outFreq, value: 1080/17 MHz}
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- {id: SAI1_MCLK2.outFreq, value: 1080/17 MHz}
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- {id: SAI1_MCLK3.outFreq, value: 30 MHz}
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- {id: SAI2_CLK_ROOT.outFreq, value: 1080/17 MHz}
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- {id: SAI2_MCLK1.outFreq, value: 1080/17 MHz}
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- {id: SAI2_MCLK3.outFreq, value: 30 MHz}
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- {id: SAI3_CLK_ROOT.outFreq, value: 1080/17 MHz}
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- {id: SAI3_MCLK1.outFreq, value: 1080/17 MHz}
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- {id: SAI3_MCLK3.outFreq, value: 30 MHz}
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- {id: SPDIF0_CLK_ROOT.outFreq, value: 30 MHz}
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- {id: TRACE_CLK_ROOT.outFreq, value: 352/3 MHz}
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- {id: UART_CLK_ROOT.outFreq, value: 80 MHz}
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- {id: USBPHY1_CLK.outFreq, value: 480 MHz}
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settings:
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- {id: CCM.AHB_PODF.scale, value: '1', locked: true}
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- {id: CCM.ARM_PODF.scale, value: '1', locked: true}
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- {id: CCM.CLKO2_SEL.sel, value: CCM.LPI2C_CLK_ROOT}
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- {id: CCM.FLEXSPI_PODF.scale, value: '2', locked: true}
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- {id: CCM.FLEXSPI_SEL.sel, value: CCM_ANALOG.PLL3_PFD0_CLK}
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- {id: CCM.IPG_PODF.scale, value: '4'}
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- {id: CCM.LPSPI_PODF.scale, value: '5', locked: true}
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- {id: CCM.PERCLK_PODF.scale, value: '2', locked: true}
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- {id: CCM.PRE_PERIPH_CLK_SEL.sel, value: CCM.ARM_PODF}
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- {id: CCM.SEMC_PODF.scale, value: '2'}
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- {id: CCM.TRACE_PODF.scale, value: '3', locked: true}
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- {id: CCM_ANALOG.PLL2.denom, value: '1', locked: true}
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- {id: CCM_ANALOG.PLL2.num, value: '0', locked: true}
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- {id: CCM_ANALOG.PLL2_BYPASS.sel, value: CCM_ANALOG.PLL2_OUT_CLK}
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- {id: CCM_ANALOG.PLL2_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD0}
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- {id: CCM_ANALOG.PLL2_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD1}
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- {id: CCM_ANALOG.PLL2_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD2}
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- {id: CCM_ANALOG.PLL2_PFD2_DIV.scale, value: '18', locked: true}
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- {id: CCM_ANALOG.PLL2_PFD2_MUL.scale, value: '18', locked: true}
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- {id: CCM_ANALOG.PLL2_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD3}
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- {id: CCM_ANALOG.PLL2_PFD3_DIV.scale, value: '18', locked: true}
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- {id: CCM_ANALOG.PLL2_PFD3_MUL.scale, value: '18', locked: true}
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- {id: CCM_ANALOG.PLL3_BYPASS.sel, value: CCM_ANALOG.PLL3}
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- {id: CCM_ANALOG.PLL3_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD0}
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- {id: CCM_ANALOG.PLL3_PFD0_DIV.scale, value: '22', locked: true}
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- {id: CCM_ANALOG.PLL3_PFD0_MUL.scale, value: '18', locked: true}
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- {id: CCM_ANALOG.PLL3_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD1}
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- {id: CCM_ANALOG.PLL3_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD2}
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- {id: CCM_ANALOG.PLL3_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD3}
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- {id: CCM_ANALOG.PLL3_PFD3_DIV.scale, value: '18', locked: true}
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- {id: CCM_ANALOG.PLL3_PFD3_MUL.scale, value: '18', locked: true}
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- {id: CCM_ANALOG.PLL4.denom, value: '50'}
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- {id: CCM_ANALOG.PLL4.div, value: '47'}
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- {id: CCM_ANALOG.PLL6_BYPASS.sel, value: CCM_ANALOG.PLL6}
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- {id: CCM_ANALOG_PLL_USB1_EN_USB_CLKS_CFG, value: Enabled}
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- {id: CCM_ANALOG_PLL_USB1_EN_USB_CLKS_OUT_CFG, value: Enabled}
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- {id: CCM_ANALOG_PLL_USB1_POWER_CFG, value: 'Yes'}
|
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sources:
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- {id: XTALOSC24M.RTC_OSC.outFreq, value: 32.768 kHz, enabled: true}
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* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
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/*******************************************************************************
|
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* Variables for BOARD_BootClockRUN configuration
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******************************************************************************/
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const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN =
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{
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.loopDivider = 1, /* PLL loop divider, Fout = Fin * ( 20 + loopDivider*2 + numerator / denominator ) */
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.numerator = 0, /* 30 bit numerator of fractional loop divider */
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.denominator = 1, /* 30 bit denominator of fractional loop divider */
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||||
.src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
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};
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const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN =
|
||||
{
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||||
.loopDivider = 0, /* PLL loop divider, Fout = Fin * 20 */
|
||||
.src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
|
||||
};
|
||||
const clock_enet_pll_config_t enetPllConfig_BOARD_BootClockRUN =
|
||||
{
|
||||
.enableClkOutput500M = true, /* Enable the PLL providing the ENET 500MHz reference clock */
|
||||
.src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
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||||
};
|
||||
/*******************************************************************************
|
||||
* Code for BOARD_BootClockRUN configuration
|
||||
******************************************************************************/
|
||||
void BOARD_BootClockRUN(void)
|
||||
{
|
||||
/* Init RTC OSC clock frequency. */
|
||||
CLOCK_SetRtcXtalFreq(32768U);
|
||||
/* Enable 1MHz clock output. */
|
||||
XTALOSC24M->OSC_CONFIG2 |= XTALOSC24M_OSC_CONFIG2_ENABLE_1M_MASK;
|
||||
/* Use free 1MHz clock output. */
|
||||
XTALOSC24M->OSC_CONFIG2 &= ~XTALOSC24M_OSC_CONFIG2_MUX_1M_MASK;
|
||||
/* Set XTAL 24MHz clock frequency. */
|
||||
CLOCK_SetXtalFreq(24000000U);
|
||||
/* Enable XTAL 24MHz clock source. */
|
||||
CLOCK_InitExternalClk(0);
|
||||
/* Enable internal RC. */
|
||||
CLOCK_InitRcOsc24M();
|
||||
/* Switch clock source to external OSC. */
|
||||
CLOCK_SwitchOsc(kCLOCK_XtalOsc);
|
||||
/* Set Oscillator ready counter value. */
|
||||
CCM->CCR = (CCM->CCR & (~CCM_CCR_OSCNT_MASK)) | CCM_CCR_OSCNT(127);
|
||||
/* Setting PeriphClk2Mux and PeriphMux to provide stable clock before PLLs are initialed */
|
||||
CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 1); /* Set PERIPH_CLK2 MUX to OSC */
|
||||
CLOCK_SetMux(kCLOCK_PeriphMux, 1); /* Set PERIPH_CLK MUX to PERIPH_CLK2 */
|
||||
/* Setting the VDD_SOC to 1.25V. It is necessary to config AHB to 500Mhz. */
|
||||
DCDC->REG3 = (DCDC->REG3 & (~DCDC_REG3_TRG_MASK)) | DCDC_REG3_TRG(0x12);
|
||||
/* Waiting for DCDC_STS_DC_OK bit is asserted */
|
||||
while (DCDC_REG0_STS_DC_OK_MASK != (DCDC_REG0_STS_DC_OK_MASK & DCDC->REG0))
|
||||
{
|
||||
}
|
||||
/* Set AHB_PODF. */
|
||||
CLOCK_SetDiv(kCLOCK_AhbDiv, 0);
|
||||
/* Disable IPG clock gate. */
|
||||
CLOCK_DisableClock(kCLOCK_Adc1);
|
||||
CLOCK_DisableClock(kCLOCK_Xbar1);
|
||||
CLOCK_DisableClock(kCLOCK_Xbar2);
|
||||
/* Set IPG_PODF. */
|
||||
CLOCK_SetDiv(kCLOCK_IpgDiv, 3);
|
||||
/* Set ARM_PODF. */
|
||||
CLOCK_SetDiv(kCLOCK_ArmDiv, 0);
|
||||
/* Set PERIPH_CLK2_PODF. */
|
||||
CLOCK_SetDiv(kCLOCK_PeriphClk2Div, 0);
|
||||
/* Disable PERCLK clock gate. */
|
||||
CLOCK_DisableClock(kCLOCK_Gpt1);
|
||||
CLOCK_DisableClock(kCLOCK_Gpt1S);
|
||||
CLOCK_DisableClock(kCLOCK_Gpt2);
|
||||
CLOCK_DisableClock(kCLOCK_Gpt2S);
|
||||
CLOCK_DisableClock(kCLOCK_Pit);
|
||||
/* Set PERCLK_PODF. */
|
||||
CLOCK_SetDiv(kCLOCK_PerclkDiv, 1);
|
||||
/* Set SEMC_PODF. */
|
||||
CLOCK_SetDiv(kCLOCK_SemcDiv, 1);
|
||||
/* Set Semc alt clock source. */
|
||||
CLOCK_SetMux(kCLOCK_SemcAltMux, 0);
|
||||
/* Set Semc clock source. */
|
||||
CLOCK_SetMux(kCLOCK_SemcMux, 0);
|
||||
/* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd.
|
||||
* With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged.
|
||||
* Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/
|
||||
#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1))
|
||||
/* Disable Flexspi clock gate. */
|
||||
CLOCK_DisableClock(kCLOCK_FlexSpi);
|
||||
/* Set FLEXSPI_PODF. */
|
||||
CLOCK_SetDiv(kCLOCK_FlexspiDiv, 1);
|
||||
/* Set Flexspi clock source. */
|
||||
CLOCK_SetMux(kCLOCK_FlexspiMux, 3);
|
||||
#endif
|
||||
/* Disable LPSPI clock gate. */
|
||||
CLOCK_DisableClock(kCLOCK_Lpspi1);
|
||||
CLOCK_DisableClock(kCLOCK_Lpspi2);
|
||||
/* Set LPSPI_PODF. */
|
||||
CLOCK_SetDiv(kCLOCK_LpspiDiv, 4);
|
||||
/* Set Lpspi clock source. */
|
||||
CLOCK_SetMux(kCLOCK_LpspiMux, 2);
|
||||
/* Disable TRACE clock gate. */
|
||||
CLOCK_DisableClock(kCLOCK_Trace);
|
||||
/* Set TRACE_PODF. */
|
||||
CLOCK_SetDiv(kCLOCK_TraceDiv, 2);
|
||||
/* Set Trace clock source. */
|
||||
CLOCK_SetMux(kCLOCK_TraceMux, 2);
|
||||
/* Disable SAI1 clock gate. */
|
||||
CLOCK_DisableClock(kCLOCK_Sai1);
|
||||
/* Set SAI1_CLK_PRED. */
|
||||
CLOCK_SetDiv(kCLOCK_Sai1PreDiv, 3);
|
||||
/* Set SAI1_CLK_PODF. */
|
||||
CLOCK_SetDiv(kCLOCK_Sai1Div, 1);
|
||||
/* Set Sai1 clock source. */
|
||||
CLOCK_SetMux(kCLOCK_Sai1Mux, 0);
|
||||
/* Disable SAI2 clock gate. */
|
||||
CLOCK_DisableClock(kCLOCK_Sai2);
|
||||
/* Set SAI2_CLK_PRED. */
|
||||
CLOCK_SetDiv(kCLOCK_Sai2PreDiv, 3);
|
||||
/* Set SAI2_CLK_PODF. */
|
||||
CLOCK_SetDiv(kCLOCK_Sai2Div, 1);
|
||||
/* Set Sai2 clock source. */
|
||||
CLOCK_SetMux(kCLOCK_Sai2Mux, 0);
|
||||
/* Disable SAI3 clock gate. */
|
||||
CLOCK_DisableClock(kCLOCK_Sai3);
|
||||
/* Set SAI3_CLK_PRED. */
|
||||
CLOCK_SetDiv(kCLOCK_Sai3PreDiv, 3);
|
||||
/* Set SAI3_CLK_PODF. */
|
||||
CLOCK_SetDiv(kCLOCK_Sai3Div, 1);
|
||||
/* Set Sai3 clock source. */
|
||||
CLOCK_SetMux(kCLOCK_Sai3Mux, 0);
|
||||
/* Disable Lpi2c clock gate. */
|
||||
CLOCK_DisableClock(kCLOCK_Lpi2c1);
|
||||
CLOCK_DisableClock(kCLOCK_Lpi2c2);
|
||||
/* Set LPI2C_CLK_PODF. */
|
||||
CLOCK_SetDiv(kCLOCK_Lpi2cDiv, 0);
|
||||
/* Set Lpi2c clock source. */
|
||||
CLOCK_SetMux(kCLOCK_Lpi2cMux, 0);
|
||||
/* Disable UART clock gate. */
|
||||
CLOCK_DisableClock(kCLOCK_Lpuart1);
|
||||
CLOCK_DisableClock(kCLOCK_Lpuart2);
|
||||
CLOCK_DisableClock(kCLOCK_Lpuart3);
|
||||
CLOCK_DisableClock(kCLOCK_Lpuart4);
|
||||
/* Set UART_CLK_PODF. */
|
||||
CLOCK_SetDiv(kCLOCK_UartDiv, 0);
|
||||
/* Set Uart clock source. */
|
||||
CLOCK_SetMux(kCLOCK_UartMux, 0);
|
||||
/* Disable SPDIF clock gate. */
|
||||
CLOCK_DisableClock(kCLOCK_Spdif);
|
||||
/* Set SPDIF0_CLK_PRED. */
|
||||
CLOCK_SetDiv(kCLOCK_Spdif0PreDiv, 1);
|
||||
/* Set SPDIF0_CLK_PODF. */
|
||||
CLOCK_SetDiv(kCLOCK_Spdif0Div, 7);
|
||||
/* Set Spdif clock source. */
|
||||
CLOCK_SetMux(kCLOCK_SpdifMux, 3);
|
||||
/* Disable Flexio1 clock gate. */
|
||||
CLOCK_DisableClock(kCLOCK_Flexio1);
|
||||
/* Set FLEXIO1_CLK_PRED. */
|
||||
CLOCK_SetDiv(kCLOCK_Flexio1PreDiv, 1);
|
||||
/* Set FLEXIO1_CLK_PODF. */
|
||||
CLOCK_SetDiv(kCLOCK_Flexio1Div, 7);
|
||||
/* Set Flexio1 clock source. */
|
||||
CLOCK_SetMux(kCLOCK_Flexio1Mux, 3);
|
||||
/* Set Pll3 sw clock source. */
|
||||
CLOCK_SetMux(kCLOCK_Pll3SwMux, 0);
|
||||
/* Init System PLL. */
|
||||
CLOCK_InitSysPll(&sysPllConfig_BOARD_BootClockRUN);
|
||||
/* Init System pfd0. */
|
||||
CLOCK_InitSysPfd(kCLOCK_Pfd0, 27);
|
||||
/* Init System pfd1. */
|
||||
CLOCK_InitSysPfd(kCLOCK_Pfd1, 16);
|
||||
/* Init System pfd2. */
|
||||
CLOCK_InitSysPfd(kCLOCK_Pfd2, 18);
|
||||
/* Init System pfd3. */
|
||||
CLOCK_InitSysPfd(kCLOCK_Pfd3, 18);
|
||||
/* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd.
|
||||
* With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged.
|
||||
* Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/
|
||||
#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1))
|
||||
/* Init Usb1 PLL. */
|
||||
CLOCK_InitUsb1Pll(&usb1PllConfig_BOARD_BootClockRUN);
|
||||
/* Init Usb1 pfd0. */
|
||||
CLOCK_InitUsb1Pfd(kCLOCK_Pfd0, 22);
|
||||
/* Init Usb1 pfd1. */
|
||||
CLOCK_InitUsb1Pfd(kCLOCK_Pfd1, 16);
|
||||
/* Init Usb1 pfd2. */
|
||||
CLOCK_InitUsb1Pfd(kCLOCK_Pfd2, 17);
|
||||
/* Init Usb1 pfd3. */
|
||||
CLOCK_InitUsb1Pfd(kCLOCK_Pfd3, 18);
|
||||
#endif
|
||||
/* DeInit Audio PLL. */
|
||||
CLOCK_DeinitAudioPll();
|
||||
/* Bypass Audio PLL. */
|
||||
CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllAudio, 1);
|
||||
/* Set divider for Audio PLL. */
|
||||
CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK;
|
||||
CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK;
|
||||
/* Enable Audio PLL output. */
|
||||
CCM_ANALOG->PLL_AUDIO |= CCM_ANALOG_PLL_AUDIO_ENABLE_MASK;
|
||||
/* Init Enet PLL. */
|
||||
CLOCK_InitEnetPll(&enetPllConfig_BOARD_BootClockRUN);
|
||||
/* Set preperiph clock source. */
|
||||
CLOCK_SetMux(kCLOCK_PrePeriphMux, 3);
|
||||
/* Set periph clock source. */
|
||||
CLOCK_SetMux(kCLOCK_PeriphMux, 0);
|
||||
/* Set periph clock2 clock source. */
|
||||
CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 0);
|
||||
/* Set per clock source. */
|
||||
CLOCK_SetMux(kCLOCK_PerclkMux, 0);
|
||||
/* Set clock out1 divider. */
|
||||
CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_DIV_MASK)) | CCM_CCOSR_CLKO1_DIV(0);
|
||||
/* Set clock out1 source. */
|
||||
CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_SEL_MASK)) | CCM_CCOSR_CLKO1_SEL(1);
|
||||
/* Set clock out2 divider. */
|
||||
CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_DIV_MASK)) | CCM_CCOSR_CLKO2_DIV(0);
|
||||
/* Set clock out2 source. */
|
||||
CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_SEL_MASK)) | CCM_CCOSR_CLKO2_SEL(6);
|
||||
/* Set clock out1 drives clock out1. */
|
||||
CCM->CCOSR &= ~CCM_CCOSR_CLK_OUT_SEL_MASK;
|
||||
/* Disable clock out1. */
|
||||
CCM->CCOSR &= ~CCM_CCOSR_CLKO1_EN_MASK;
|
||||
/* Disable clock out2. */
|
||||
CCM->CCOSR &= ~CCM_CCOSR_CLKO2_EN_MASK;
|
||||
/* Set SAI1 MCLK1 clock source. */
|
||||
IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk1Sel, 0);
|
||||
/* Set SAI1 MCLK2 clock source. */
|
||||
IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk2Sel, 0);
|
||||
/* Set SAI1 MCLK3 clock source. */
|
||||
IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk3Sel, 0);
|
||||
/* Set SAI2 MCLK3 clock source. */
|
||||
IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI2MClk3Sel, 0);
|
||||
/* Set SAI3 MCLK3 clock source. */
|
||||
IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI3MClk3Sel, 0);
|
||||
/* Set MQS configuration. */
|
||||
IOMUXC_MQSConfig(IOMUXC_GPR,kIOMUXC_MqsPwmOverSampleRate32, 0);
|
||||
/* Set GPT1 High frequency reference clock source. */
|
||||
IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK;
|
||||
/* Set GPT2 High frequency reference clock source. */
|
||||
IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK;
|
||||
/* Set SystemCoreClock variable. */
|
||||
SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK;
|
||||
}
|
||||
+100
@@ -0,0 +1,100 @@
|
||||
#ifndef _CLOCK_CONFIG_H_
|
||||
#define _CLOCK_CONFIG_H_
|
||||
|
||||
#include "fsl_common.h"
|
||||
|
||||
/*******************************************************************************
|
||||
* Definitions
|
||||
******************************************************************************/
|
||||
#define BOARD_XTAL0_CLK_HZ 24000000U /*!< Board xtal0 frequency in Hz */
|
||||
|
||||
#define BOARD_XTAL32K_CLK_HZ 32768U /*!< Board xtal32k frequency in Hz */
|
||||
/*******************************************************************************
|
||||
************************ BOARD_InitBootClocks function ************************
|
||||
******************************************************************************/
|
||||
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
#endif /* __cplusplus*/
|
||||
|
||||
/*!
|
||||
* @brief This function executes default configuration of clocks.
|
||||
*
|
||||
*/
|
||||
void BOARD_InitBootClocks(void);
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif /* __cplusplus*/
|
||||
|
||||
/*******************************************************************************
|
||||
********************** Configuration BOARD_BootClockRUN ***********************
|
||||
******************************************************************************/
|
||||
/*******************************************************************************
|
||||
* Definitions for BOARD_BootClockRUN configuration
|
||||
******************************************************************************/
|
||||
#define BOARD_BOOTCLOCKRUN_CORE_CLOCK 500000000U /*!< Core clock frequency: 500000000Hz */
|
||||
|
||||
/* Clock outputs (values are in Hz): */
|
||||
#define BOARD_BOOTCLOCKRUN_AHB_CLK_ROOT 500000000UL /* Clock consumers of AHB_CLK_ROOT output : AIPSTZ1, AIPSTZ2, AIPSTZ3, AIPSTZ4, ARM, FLEXSPI */
|
||||
#define BOARD_BOOTCLOCKRUN_CKIL_SYNC_CLK_ROOT 32768UL /* Clock consumers of CKIL_SYNC_CLK_ROOT output : CSU, EWM, GPT1, GPT2, KPP, PIT, RTWDOG, SNVS, SPDIF, TEMPMON, USB, WDOG1, WDOG2 */
|
||||
#define BOARD_BOOTCLOCKRUN_CLKO1_CLK 0UL /* Clock consumers of CLKO1_CLK output : N/A */
|
||||
#define BOARD_BOOTCLOCKRUN_CLKO2_CLK 0UL /* Clock consumers of CLKO2_CLK output : N/A */
|
||||
#define BOARD_BOOTCLOCKRUN_CLK_1M 1000000UL /* Clock consumers of CLK_1M output : EWM, RTWDOG */
|
||||
#define BOARD_BOOTCLOCKRUN_CLK_24M 24000000UL /* Clock consumers of CLK_24M output : GPT1, GPT2 */
|
||||
#define BOARD_BOOTCLOCKRUN_ENET_500M_REF_CLK 500000000UL /* Clock consumers of ENET_500M_REF_CLK output : N/A */
|
||||
#define BOARD_BOOTCLOCKRUN_FLEXIO1_CLK_ROOT 30000000UL /* Clock consumers of FLEXIO1_CLK_ROOT output : FLEXIO1 */
|
||||
#define BOARD_BOOTCLOCKRUN_FLEXSPI_CLK_ROOT 196363636UL /* Clock consumers of FLEXSPI_CLK_ROOT output : FLEXSPI */
|
||||
#define BOARD_BOOTCLOCKRUN_GPT1_IPG_CLK_HIGHFREQ 62500000UL /* Clock consumers of GPT1_ipg_clk_highfreq output : GPT1 */
|
||||
#define BOARD_BOOTCLOCKRUN_GPT2_IPG_CLK_HIGHFREQ 62500000UL /* Clock consumers of GPT2_ipg_clk_highfreq output : GPT2 */
|
||||
#define BOARD_BOOTCLOCKRUN_IPG_CLK_ROOT 125000000UL /* Clock consumers of IPG_CLK_ROOT output : ADC1, ADC_ETC, AOI, ARM, BEE, CCM, CSU, DCDC, DCP, DMA0, DMAMUX, ENC1, EWM, FLEXIO1, FLEXRAM, FLEXSPI, GPC, GPIO1, GPIO2, GPIO3, GPIO5, IOMUXC, KPP, LPI2C1, LPI2C2, LPSPI1, LPSPI2, LPUART1, LPUART2, LPUART3, LPUART4, NVIC, OCOTP, PWM1, RTWDOG, SAI1, SAI2, SAI3, SNVS, SPDIF, SRC, TEMPMON, TMR1, TRNG, USB, WDOG1, WDOG2, XBARA, XBARB */
|
||||
#define BOARD_BOOTCLOCKRUN_LPI2C_CLK_ROOT 60000000UL /* Clock consumers of LPI2C_CLK_ROOT output : LPI2C1, LPI2C2 */
|
||||
#define BOARD_BOOTCLOCKRUN_LPSPI_CLK_ROOT 105600000UL /* Clock consumers of LPSPI_CLK_ROOT output : LPSPI1, LPSPI2 */
|
||||
#define BOARD_BOOTCLOCKRUN_MQS_MCLK 63529411UL /* Clock consumers of MQS_MCLK output : N/A */
|
||||
#define BOARD_BOOTCLOCKRUN_PERCLK_CLK_ROOT 62500000UL /* Clock consumers of PERCLK_CLK_ROOT output : GPT1, GPT2, PIT */
|
||||
#define BOARD_BOOTCLOCKRUN_SAI1_CLK_ROOT 63529411UL /* Clock consumers of SAI1_CLK_ROOT output : N/A */
|
||||
#define BOARD_BOOTCLOCKRUN_SAI1_MCLK1 63529411UL /* Clock consumers of SAI1_MCLK1 output : SAI1 */
|
||||
#define BOARD_BOOTCLOCKRUN_SAI1_MCLK2 63529411UL /* Clock consumers of SAI1_MCLK2 output : SAI1 */
|
||||
#define BOARD_BOOTCLOCKRUN_SAI1_MCLK3 30000000UL /* Clock consumers of SAI1_MCLK3 output : SAI1 */
|
||||
#define BOARD_BOOTCLOCKRUN_SAI2_CLK_ROOT 63529411UL /* Clock consumers of SAI2_CLK_ROOT output : N/A */
|
||||
#define BOARD_BOOTCLOCKRUN_SAI2_MCLK1 63529411UL /* Clock consumers of SAI2_MCLK1 output : SAI2 */
|
||||
#define BOARD_BOOTCLOCKRUN_SAI2_MCLK2 0UL /* Clock consumers of SAI2_MCLK2 output : SAI2 */
|
||||
#define BOARD_BOOTCLOCKRUN_SAI2_MCLK3 30000000UL /* Clock consumers of SAI2_MCLK3 output : SAI2 */
|
||||
#define BOARD_BOOTCLOCKRUN_SAI3_CLK_ROOT 63529411UL /* Clock consumers of SAI3_CLK_ROOT output : N/A */
|
||||
#define BOARD_BOOTCLOCKRUN_SAI3_MCLK1 63529411UL /* Clock consumers of SAI3_MCLK1 output : SAI3 */
|
||||
#define BOARD_BOOTCLOCKRUN_SAI3_MCLK2 0UL /* Clock consumers of SAI3_MCLK2 output : SAI3 */
|
||||
#define BOARD_BOOTCLOCKRUN_SAI3_MCLK3 30000000UL /* Clock consumers of SAI3_MCLK3 output : SAI3 */
|
||||
#define BOARD_BOOTCLOCKRUN_SPDIF0_CLK_ROOT 30000000UL /* Clock consumers of SPDIF0_CLK_ROOT output : SPDIF */
|
||||
#define BOARD_BOOTCLOCKRUN_SPDIF0_EXTCLK_OUT 0UL /* Clock consumers of SPDIF0_EXTCLK_OUT output : SPDIF */
|
||||
#define BOARD_BOOTCLOCKRUN_TRACE_CLK_ROOT 117333333UL /* Clock consumers of TRACE_CLK_ROOT output : ARM */
|
||||
#define BOARD_BOOTCLOCKRUN_UART_CLK_ROOT 80000000UL /* Clock consumers of UART_CLK_ROOT output : LPUART1, LPUART2, LPUART3, LPUART4 */
|
||||
#define BOARD_BOOTCLOCKRUN_USBPHY1_CLK 480000000UL /* Clock consumers of USBPHY1_CLK output : TEMPMON, USB */
|
||||
|
||||
/*! @brief Usb1 PLL set for BOARD_BootClockRUN configuration.
|
||||
*/
|
||||
extern const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN;
|
||||
/*! @brief Sys PLL for BOARD_BootClockRUN configuration.
|
||||
*/
|
||||
extern const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN;
|
||||
/*! @brief Enet PLL set for BOARD_BootClockRUN configuration.
|
||||
*/
|
||||
extern const clock_enet_pll_config_t enetPllConfig_BOARD_BootClockRUN;
|
||||
|
||||
/*******************************************************************************
|
||||
* API for BOARD_BootClockRUN configuration
|
||||
******************************************************************************/
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
#endif /* __cplusplus*/
|
||||
|
||||
/*!
|
||||
* @brief This function executes configuration of clocks.
|
||||
*
|
||||
*/
|
||||
void BOARD_BootClockRUN(void);
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif /* __cplusplus*/
|
||||
|
||||
#endif /* _CLOCK_CONFIG_H_ */
|
||||
+137
@@ -0,0 +1,137 @@
|
||||
/***********************************************************************************************************************
|
||||
* This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
|
||||
* will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
|
||||
**********************************************************************************************************************/
|
||||
|
||||
/*
|
||||
* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
|
||||
!!GlobalInfo
|
||||
product: Pins v17.0
|
||||
processor: MIMXRT1015xxxxx
|
||||
package_id: MIMXRT1015DAF5A
|
||||
mcu_data: ksdk2_0
|
||||
processor_version: 24.12.10
|
||||
board: MIMXRT1015-EVK
|
||||
external_user_signals: {}
|
||||
pin_labels:
|
||||
- {pin_num: '21', pin_signal: GPIO_SD_B1_01, label: GPIO SD_B1_01, identifier: USER_LED}
|
||||
power_domains: {NVCC_GPIO: '3.3'}
|
||||
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
|
||||
*/
|
||||
|
||||
#include "fsl_common.h"
|
||||
#include "fsl_iomuxc.h"
|
||||
#include "fsl_gpio.h"
|
||||
#include "pin_mux.h"
|
||||
|
||||
/* FUNCTION ************************************************************************************************************
|
||||
*
|
||||
* Function Name : BOARD_InitBootPins
|
||||
* Description : Calls initialization functions.
|
||||
*
|
||||
* END ****************************************************************************************************************/
|
||||
void BOARD_InitBootPins(void) {
|
||||
BOARD_InitPins();
|
||||
BOARD_InitDEBUG_UARTPins();
|
||||
}
|
||||
|
||||
/*
|
||||
* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
|
||||
BOARD_InitPins:
|
||||
- options: {callFromInitBoot: 'true', coreID: core0, enableClock: 'true'}
|
||||
- pin_list:
|
||||
- {pin_num: '1', peripheral: GPIO2, signal: 'gpio_io, 09', pin_signal: GPIO_EMC_09, direction: INPUT, pull_keeper_select: Pull, pull_up_down_config: Pull_Up_47K_Ohm}
|
||||
- {pin_num: '21', peripheral: GPIO3, signal: 'gpio_io, 21', pin_signal: GPIO_SD_B1_01, direction: OUTPUT}
|
||||
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
|
||||
*/
|
||||
|
||||
/* FUNCTION ************************************************************************************************************
|
||||
*
|
||||
* Function Name : BOARD_InitPins
|
||||
* Description : Configures pin routing and optionally pin electrical features.
|
||||
*
|
||||
* END ****************************************************************************************************************/
|
||||
void BOARD_InitPins(void) {
|
||||
CLOCK_EnableClock(kCLOCK_Iomuxc);
|
||||
|
||||
/* GPIO configuration of USER_BUTTON on GPIO_EMC_09 (pin 1) */
|
||||
gpio_pin_config_t USER_BUTTON_config = {
|
||||
.direction = kGPIO_DigitalInput,
|
||||
.outputLogic = 0U,
|
||||
.interruptMode = kGPIO_NoIntmode
|
||||
};
|
||||
/* Initialize GPIO functionality on GPIO_EMC_09 (pin 1) */
|
||||
GPIO_PinInit(GPIO2, 9U, &USER_BUTTON_config);
|
||||
|
||||
/* GPIO configuration of USER_LED on GPIO_SD_B1_01 (pin 21) */
|
||||
gpio_pin_config_t USER_LED_config = {
|
||||
.direction = kGPIO_DigitalOutput,
|
||||
.outputLogic = 0U,
|
||||
.interruptMode = kGPIO_NoIntmode
|
||||
};
|
||||
/* Initialize GPIO functionality on GPIO_SD_B1_01 (pin 21) */
|
||||
GPIO_PinInit(GPIO3, 21U, &USER_LED_config);
|
||||
|
||||
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_09_GPIO2_IO09, 0U);
|
||||
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_01_GPIO3_IO21, 0U);
|
||||
IOMUXC_SetPinConfig(IOMUXC_GPIO_EMC_09_GPIO2_IO09, 0x70B0U);
|
||||
}
|
||||
|
||||
/*
|
||||
* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
|
||||
BOARD_InitQSPIPins:
|
||||
- options: {callFromInitBoot: 'false', coreID: core0, enableClock: 'true'}
|
||||
- pin_list:
|
||||
- {pin_num: '12', peripheral: FLEXSPI, signal: FLEXSPI_A_SCLK, pin_signal: GPIO_SD_B1_07}
|
||||
- {pin_num: '11', peripheral: FLEXSPI, signal: FLEXSPI_A_DATA0, pin_signal: GPIO_SD_B1_08}
|
||||
- {pin_num: '9', peripheral: FLEXSPI, signal: FLEXSPI_A_DATA1, pin_signal: GPIO_SD_B1_10}
|
||||
- {pin_num: '10', peripheral: FLEXSPI, signal: FLEXSPI_A_DATA2, pin_signal: GPIO_SD_B1_09}
|
||||
- {pin_num: '13', peripheral: FLEXSPI, signal: FLEXSPI_A_DATA3, pin_signal: GPIO_SD_B1_06}
|
||||
- {pin_num: '8', peripheral: FLEXSPI, signal: FLEXSPI_A_SS0_B, pin_signal: GPIO_SD_B1_11}
|
||||
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
|
||||
*/
|
||||
|
||||
/* FUNCTION ************************************************************************************************************
|
||||
*
|
||||
* Function Name : BOARD_InitQSPIPins
|
||||
* Description : Configures pin routing and optionally pin electrical features.
|
||||
*
|
||||
* END ****************************************************************************************************************/
|
||||
void BOARD_InitQSPIPins(void) {
|
||||
CLOCK_EnableClock(kCLOCK_Iomuxc);
|
||||
|
||||
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_06_FLEXSPI_A_DATA03, 0U);
|
||||
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_07_FLEXSPI_A_SCLK, 0U);
|
||||
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_08_FLEXSPI_A_DATA00, 0U);
|
||||
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_09_FLEXSPI_A_DATA02, 0U);
|
||||
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_10_FLEXSPI_A_DATA01, 0U);
|
||||
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_11_FLEXSPI_A_SS0_B, 0U);
|
||||
}
|
||||
|
||||
/*
|
||||
* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
|
||||
BOARD_InitDEBUG_UARTPins:
|
||||
- options: {callFromInitBoot: 'true', coreID: core0, enableClock: 'true'}
|
||||
- pin_list:
|
||||
- {pin_num: '68', peripheral: LPUART1, signal: RX, pin_signal: GPIO_AD_B0_07, slew_rate: Slow}
|
||||
- {pin_num: '72', peripheral: LPUART1, signal: TX, pin_signal: GPIO_AD_B0_06, slew_rate: Slow}
|
||||
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
|
||||
*/
|
||||
|
||||
/* FUNCTION ************************************************************************************************************
|
||||
*
|
||||
* Function Name : BOARD_InitDEBUG_UARTPins
|
||||
* Description : Configures pin routing and optionally pin electrical features.
|
||||
*
|
||||
* END ****************************************************************************************************************/
|
||||
void BOARD_InitDEBUG_UARTPins(void) {
|
||||
CLOCK_EnableClock(kCLOCK_Iomuxc);
|
||||
|
||||
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_06_LPUART1_TX, 0U);
|
||||
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_07_LPUART1_RX, 0U);
|
||||
IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_06_LPUART1_TX, 0x10B0U);
|
||||
IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_07_LPUART1_RX, 0x10B0U);
|
||||
}
|
||||
/***********************************************************************************************************************
|
||||
* EOF
|
||||
**********************************************************************************************************************/
|
||||
+141
@@ -0,0 +1,141 @@
|
||||
/***********************************************************************************************************************
|
||||
* This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
|
||||
* will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
|
||||
**********************************************************************************************************************/
|
||||
|
||||
#ifndef _PIN_MUX_H_
|
||||
#define _PIN_MUX_H_
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* Definitions
|
||||
**********************************************************************************************************************/
|
||||
|
||||
/*! @brief Direction type */
|
||||
typedef enum _pin_mux_direction
|
||||
{
|
||||
kPIN_MUX_DirectionInput = 0U, /* Input direction */
|
||||
kPIN_MUX_DirectionOutput = 1U, /* Output direction */
|
||||
kPIN_MUX_DirectionInputOrOutput = 2U /* Input or output direction */
|
||||
} pin_mux_direction_t;
|
||||
|
||||
/*!
|
||||
* @addtogroup pin_mux
|
||||
* @{
|
||||
*/
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* API
|
||||
**********************************************************************************************************************/
|
||||
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/*!
|
||||
* @brief Calls initialization functions.
|
||||
*
|
||||
*/
|
||||
void BOARD_InitBootPins(void);
|
||||
|
||||
/* GPIO_EMC_09 (number 1), USER_BUTTON/SW4 */
|
||||
/* Routed pin properties */
|
||||
#define BOARD_INITPINS_USER_BUTTON_PERIPHERAL GPIO2 /*!< Peripheral name */
|
||||
#define BOARD_INITPINS_USER_BUTTON_SIGNAL gpio_io /*!< Signal name */
|
||||
#define BOARD_INITPINS_USER_BUTTON_CHANNEL 9U /*!< Signal channel */
|
||||
|
||||
/* Symbols to be used with GPIO driver */
|
||||
#define BOARD_INITPINS_USER_BUTTON_GPIO GPIO2 /*!< GPIO peripheral base pointer */
|
||||
#define BOARD_INITPINS_USER_BUTTON_GPIO_PIN 9U /*!< GPIO pin number */
|
||||
#define BOARD_INITPINS_USER_BUTTON_GPIO_PIN_MASK (1U << 9U) /*!< GPIO pin mask */
|
||||
#define BOARD_INITPINS_USER_BUTTON_PORT GPIO2 /*!< PORT peripheral base pointer */
|
||||
#define BOARD_INITPINS_USER_BUTTON_PIN 9U /*!< PORT pin number */
|
||||
#define BOARD_INITPINS_USER_BUTTON_PIN_MASK (1U << 9U) /*!< PORT pin mask */
|
||||
|
||||
/* GPIO_SD_B1_01 (number 21), GPIO SD_B1_01 */
|
||||
/* Routed pin properties */
|
||||
#define BOARD_INITPINS_USER_LED_PERIPHERAL GPIO3 /*!< Peripheral name */
|
||||
#define BOARD_INITPINS_USER_LED_SIGNAL gpio_io /*!< Signal name */
|
||||
#define BOARD_INITPINS_USER_LED_CHANNEL 21U /*!< Signal channel */
|
||||
|
||||
/* Symbols to be used with GPIO driver */
|
||||
#define BOARD_INITPINS_USER_LED_GPIO GPIO3 /*!< GPIO peripheral base pointer */
|
||||
#define BOARD_INITPINS_USER_LED_INIT_GPIO_VALUE 0U /*!< GPIO output initial state */
|
||||
#define BOARD_INITPINS_USER_LED_GPIO_PIN 21U /*!< GPIO pin number */
|
||||
#define BOARD_INITPINS_USER_LED_GPIO_PIN_MASK (1U << 21U) /*!< GPIO pin mask */
|
||||
#define BOARD_INITPINS_USER_LED_PORT GPIO3 /*!< PORT peripheral base pointer */
|
||||
#define BOARD_INITPINS_USER_LED_PIN 21U /*!< PORT pin number */
|
||||
#define BOARD_INITPINS_USER_LED_PIN_MASK (1U << 21U) /*!< PORT pin mask */
|
||||
|
||||
|
||||
/*!
|
||||
* @brief Configures pin routing and optionally pin electrical features.
|
||||
*
|
||||
*/
|
||||
void BOARD_InitPins(void);
|
||||
|
||||
/* GPIO_SD_B1_07 (number 12), FlexSPI_CLK_A/U13[6] */
|
||||
/* Routed pin properties */
|
||||
#define BOARD_INITQSPIPINS_FlexSPI_CLK_PERIPHERAL FLEXSPI /*!< Peripheral name */
|
||||
#define BOARD_INITQSPIPINS_FlexSPI_CLK_SIGNAL FLEXSPI_A_SCLK /*!< Signal name */
|
||||
|
||||
/* GPIO_SD_B1_08 (number 11), FlexSPI_D0_A/U13[5] */
|
||||
/* Routed pin properties */
|
||||
#define BOARD_INITQSPIPINS_FlexSPI_D0_A_PERIPHERAL FLEXSPI /*!< Peripheral name */
|
||||
#define BOARD_INITQSPIPINS_FlexSPI_D0_A_SIGNAL FLEXSPI_A_DATA0 /*!< Signal name */
|
||||
|
||||
/* GPIO_SD_B1_10 (number 9), FlexSPI_D1_A/U13[2] */
|
||||
/* Routed pin properties */
|
||||
#define BOARD_INITQSPIPINS_FlexSPI_D1_A_PERIPHERAL FLEXSPI /*!< Peripheral name */
|
||||
#define BOARD_INITQSPIPINS_FlexSPI_D1_A_SIGNAL FLEXSPI_A_DATA1 /*!< Signal name */
|
||||
|
||||
/* GPIO_SD_B1_09 (number 10), FlexSPI_D2_A/U13[3] */
|
||||
/* Routed pin properties */
|
||||
#define BOARD_INITQSPIPINS_FlexSPI_D2_A_PERIPHERAL FLEXSPI /*!< Peripheral name */
|
||||
#define BOARD_INITQSPIPINS_FlexSPI_D2_A_SIGNAL FLEXSPI_A_DATA2 /*!< Signal name */
|
||||
|
||||
/* GPIO_SD_B1_06 (number 13), FlexSPI_D3_A/U13[7] */
|
||||
/* Routed pin properties */
|
||||
#define BOARD_INITQSPIPINS_FlexSPI_D3_A_PERIPHERAL FLEXSPI /*!< Peripheral name */
|
||||
#define BOARD_INITQSPIPINS_FlexSPI_D3_A_SIGNAL FLEXSPI_A_DATA3 /*!< Signal name */
|
||||
|
||||
/* GPIO_SD_B1_11 (number 8), FlexSPI_SS0/U13[1] */
|
||||
/* Routed pin properties */
|
||||
#define BOARD_INITQSPIPINS_FlexSPI_SS0_PERIPHERAL FLEXSPI /*!< Peripheral name */
|
||||
#define BOARD_INITQSPIPINS_FlexSPI_SS0_SIGNAL FLEXSPI_A_SS0_B /*!< Signal name */
|
||||
|
||||
|
||||
/*!
|
||||
* @brief Configures pin routing and optionally pin electrical features.
|
||||
*
|
||||
*/
|
||||
void BOARD_InitQSPIPins(void);
|
||||
|
||||
/* GPIO_AD_B0_07 (number 68), LPUART1_RXD */
|
||||
/* Routed pin properties */
|
||||
#define BOARD_INITDEBUG_UARTPINS_UART1_RXD_PERIPHERAL LPUART1 /*!< Peripheral name */
|
||||
#define BOARD_INITDEBUG_UARTPINS_UART1_RXD_SIGNAL RX /*!< Signal name */
|
||||
|
||||
/* GPIO_AD_B0_06 (number 72), LPUART1_TXD */
|
||||
/* Routed pin properties */
|
||||
#define BOARD_INITDEBUG_UARTPINS_UART1_TXD_PERIPHERAL LPUART1 /*!< Peripheral name */
|
||||
#define BOARD_INITDEBUG_UARTPINS_UART1_TXD_SIGNAL TX /*!< Signal name */
|
||||
|
||||
|
||||
/*!
|
||||
* @brief Configures pin routing and optionally pin electrical features.
|
||||
*
|
||||
*/
|
||||
void BOARD_InitDEBUG_UARTPins(void);
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
|
||||
/*!
|
||||
* @}
|
||||
*/
|
||||
#endif /* _PIN_MUX_H_ */
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* EOF
|
||||
**********************************************************************************************************************/
|
||||
Executable
+48
@@ -0,0 +1,48 @@
|
||||
/*
|
||||
* Copyright 2018-2019 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include "evkmimxrt1015_flexspi_nor_config.h"
|
||||
|
||||
/* Component ID definition, used by tools. */
|
||||
#ifndef FSL_COMPONENT_ID
|
||||
#define FSL_COMPONENT_ID "platform.drivers.xip_board"
|
||||
#endif
|
||||
|
||||
/*******************************************************************************
|
||||
* Code
|
||||
******************************************************************************/
|
||||
#if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1)
|
||||
#if defined(__CC_ARM) || defined(__ARMCC_VERSION) || defined(__GNUC__)
|
||||
__attribute__((section(".boot_hdr.conf")))
|
||||
#elif defined(__ICCARM__)
|
||||
#pragma location = ".boot_hdr.conf"
|
||||
#endif
|
||||
|
||||
const flexspi_nor_config_t qspiflash_config = {
|
||||
.memConfig =
|
||||
{
|
||||
.tag = FLEXSPI_CFG_BLK_TAG,
|
||||
.version = FLEXSPI_CFG_BLK_VERSION,
|
||||
.readSampleClkSrc = kFlexSPIReadSampleClk_LoopbackFromDqsPad,
|
||||
.csHoldTime = 3u,
|
||||
.csSetupTime = 3u,
|
||||
.sflashPadType = kSerialFlash_4Pads,
|
||||
.serialClkFreq = kFlexSpiSerialClk_100MHz,
|
||||
.sflashA1Size = 16u * 1024u * 1024u,
|
||||
.lookupTable =
|
||||
{
|
||||
// Read LUTs
|
||||
FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEB, RADDR_SDR, FLEXSPI_4PAD, 0x18),
|
||||
FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 0x06, READ_SDR, FLEXSPI_4PAD, 0x04),
|
||||
},
|
||||
},
|
||||
.pageSize = 256u,
|
||||
.sectorSize = 4u * 1024u,
|
||||
.blockSize = 256u * 1024u,
|
||||
.isUniformBlockSize = false,
|
||||
};
|
||||
#endif /* XIP_BOOT_HEADER_ENABLE */
|
||||
Executable
+268
@@ -0,0 +1,268 @@
|
||||
/*
|
||||
* Copyright 2018-2019 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef __EVKMIMXRT1015_FLEXSPI_NOR_CONFIG__
|
||||
#define __EVKMIMXRT1015_FLEXSPI_NOR_CONFIG__
|
||||
|
||||
#include <stdint.h>
|
||||
#include <stdbool.h>
|
||||
#include "fsl_common.h"
|
||||
|
||||
/*! @name Driver version */
|
||||
/*@{*/
|
||||
/*! @brief XIP_BOARD driver version 2.0.0. */
|
||||
#define FSL_XIP_BOARD_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
|
||||
/*@}*/
|
||||
|
||||
/* FLEXSPI memory config block related definitions */
|
||||
#define FLEXSPI_CFG_BLK_TAG (0x42464346UL) // ascii "FCFB" Big Endian
|
||||
#define FLEXSPI_CFG_BLK_VERSION (0x56010400UL) // V1.4.0
|
||||
#define FLEXSPI_CFG_BLK_SIZE (512)
|
||||
|
||||
/* FLEXSPI Feature related definitions */
|
||||
#define FLEXSPI_FEATURE_HAS_PARALLEL_MODE 1
|
||||
|
||||
/* Lookup table related definitions */
|
||||
#define CMD_INDEX_READ 0
|
||||
#define CMD_INDEX_READSTATUS 1
|
||||
#define CMD_INDEX_WRITEENABLE 2
|
||||
#define CMD_INDEX_WRITE 4
|
||||
|
||||
#define CMD_LUT_SEQ_IDX_READ 0
|
||||
#define CMD_LUT_SEQ_IDX_READSTATUS 1
|
||||
#define CMD_LUT_SEQ_IDX_WRITEENABLE 3
|
||||
#define CMD_LUT_SEQ_IDX_WRITE 9
|
||||
|
||||
#define CMD_SDR 0x01
|
||||
#define CMD_DDR 0x21
|
||||
#define RADDR_SDR 0x02
|
||||
#define RADDR_DDR 0x22
|
||||
#define CADDR_SDR 0x03
|
||||
#define CADDR_DDR 0x23
|
||||
#define MODE1_SDR 0x04
|
||||
#define MODE1_DDR 0x24
|
||||
#define MODE2_SDR 0x05
|
||||
#define MODE2_DDR 0x25
|
||||
#define MODE4_SDR 0x06
|
||||
#define MODE4_DDR 0x26
|
||||
#define MODE8_SDR 0x07
|
||||
#define MODE8_DDR 0x27
|
||||
#define WRITE_SDR 0x08
|
||||
#define WRITE_DDR 0x28
|
||||
#define READ_SDR 0x09
|
||||
#define READ_DDR 0x29
|
||||
#define LEARN_SDR 0x0A
|
||||
#define LEARN_DDR 0x2A
|
||||
#define DATSZ_SDR 0x0B
|
||||
#define DATSZ_DDR 0x2B
|
||||
#define DUMMY_SDR 0x0C
|
||||
#define DUMMY_DDR 0x2C
|
||||
#define DUMMY_RWDS_SDR 0x0D
|
||||
#define DUMMY_RWDS_DDR 0x2D
|
||||
#define JMP_ON_CS 0x1F
|
||||
#define STOP 0
|
||||
|
||||
#define FLEXSPI_1PAD 0
|
||||
#define FLEXSPI_2PAD 1
|
||||
#define FLEXSPI_4PAD 2
|
||||
#define FLEXSPI_8PAD 3
|
||||
|
||||
#define FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) \
|
||||
(FLEXSPI_LUT_OPERAND0(op0) | FLEXSPI_LUT_NUM_PADS0(pad0) | FLEXSPI_LUT_OPCODE0(cmd0) | FLEXSPI_LUT_OPERAND1(op1) | \
|
||||
FLEXSPI_LUT_NUM_PADS1(pad1) | FLEXSPI_LUT_OPCODE1(cmd1))
|
||||
|
||||
//!@brief Definitions for FlexSPI Serial Clock Frequency
|
||||
typedef enum _FlexSpiSerialClockFreq
|
||||
{
|
||||
kFlexSpiSerialClk_30MHz = 1,
|
||||
kFlexSpiSerialClk_50MHz = 2,
|
||||
kFlexSpiSerialClk_60MHz = 3,
|
||||
kFlexSpiSerialClk_75MHz = 4,
|
||||
kFlexSpiSerialClk_80MHz = 5,
|
||||
kFlexSpiSerialClk_100MHz = 6,
|
||||
kFlexSpiSerialClk_133MHz = 7,
|
||||
kFlexSpiSerialClk_166MHz = 8,
|
||||
kFlexSpiSerialClk_200MHz = 9,
|
||||
} flexspi_serial_clk_freq_t;
|
||||
|
||||
//!@brief FlexSPI clock configuration type
|
||||
enum
|
||||
{
|
||||
kFlexSpiClk_SDR, //!< Clock configure for SDR mode
|
||||
kFlexSpiClk_DDR, //!< Clock configurat for DDR mode
|
||||
};
|
||||
|
||||
//!@brief FlexSPI Read Sample Clock Source definition
|
||||
typedef enum _FlashReadSampleClkSource
|
||||
{
|
||||
kFlexSPIReadSampleClk_LoopbackInternally = 0,
|
||||
kFlexSPIReadSampleClk_LoopbackFromDqsPad = 1,
|
||||
kFlexSPIReadSampleClk_LoopbackFromSckPad = 2,
|
||||
kFlexSPIReadSampleClk_ExternalInputFromDqsPad = 3,
|
||||
} flexspi_read_sample_clk_t;
|
||||
|
||||
//!@brief Misc feature bit definitions
|
||||
enum
|
||||
{
|
||||
kFlexSpiMiscOffset_DiffClkEnable = 0, //!< Bit for Differential clock enable
|
||||
kFlexSpiMiscOffset_Ck2Enable = 1, //!< Bit for CK2 enable
|
||||
kFlexSpiMiscOffset_ParallelEnable = 2, //!< Bit for Parallel mode enable
|
||||
kFlexSpiMiscOffset_WordAddressableEnable = 3, //!< Bit for Word Addressable enable
|
||||
kFlexSpiMiscOffset_SafeConfigFreqEnable = 4, //!< Bit for Safe Configuration Frequency enable
|
||||
kFlexSpiMiscOffset_PadSettingOverrideEnable = 5, //!< Bit for Pad setting override enable
|
||||
kFlexSpiMiscOffset_DdrModeEnable = 6, //!< Bit for DDR clock confiuration indication.
|
||||
};
|
||||
|
||||
//!@brief Flash Type Definition
|
||||
enum
|
||||
{
|
||||
kFlexSpiDeviceType_SerialNOR = 1, //!< Flash devices are Serial NOR
|
||||
kFlexSpiDeviceType_SerialNAND = 2, //!< Flash devices are Serial NAND
|
||||
kFlexSpiDeviceType_SerialRAM = 3, //!< Flash devices are Serial RAM/HyperFLASH
|
||||
kFlexSpiDeviceType_MCP_NOR_NAND = 0x12, //!< Flash device is MCP device, A1 is Serial NOR, A2 is Serial NAND
|
||||
kFlexSpiDeviceType_MCP_NOR_RAM = 0x13, //!< Flash device is MCP device, A1 is Serial NOR, A2 is Serial RAMs
|
||||
};
|
||||
|
||||
//!@brief Flash Pad Definitions
|
||||
enum
|
||||
{
|
||||
kSerialFlash_1Pad = 1,
|
||||
kSerialFlash_2Pads = 2,
|
||||
kSerialFlash_4Pads = 4,
|
||||
kSerialFlash_8Pads = 8,
|
||||
};
|
||||
|
||||
//!@brief FlexSPI LUT Sequence structure
|
||||
typedef struct _lut_sequence
|
||||
{
|
||||
uint8_t seqNum; //!< Sequence Number, valid number: 1-16
|
||||
uint8_t seqId; //!< Sequence Index, valid number: 0-15
|
||||
uint16_t reserved;
|
||||
} flexspi_lut_seq_t;
|
||||
|
||||
//!@brief Flash Configuration Command Type
|
||||
enum
|
||||
{
|
||||
kDeviceConfigCmdType_Generic, //!< Generic command, for example: configure dummy cycles, drive strength, etc
|
||||
kDeviceConfigCmdType_QuadEnable, //!< Quad Enable command
|
||||
kDeviceConfigCmdType_Spi2Xpi, //!< Switch from SPI to DPI/QPI/OPI mode
|
||||
kDeviceConfigCmdType_Xpi2Spi, //!< Switch from DPI/QPI/OPI to SPI mode
|
||||
kDeviceConfigCmdType_Spi2NoCmd, //!< Switch to 0-4-4/0-8-8 mode
|
||||
kDeviceConfigCmdType_Reset, //!< Reset device command
|
||||
};
|
||||
|
||||
//!@brief FlexSPI Memory Configuration Block
|
||||
typedef struct _FlexSPIConfig
|
||||
{
|
||||
uint32_t tag; //!< [0x000-0x003] Tag, fixed value 0x42464346UL
|
||||
uint32_t version; //!< [0x004-0x007] Version,[31:24] -'V', [23:16] - Major, [15:8] - Minor, [7:0] - bugfix
|
||||
uint32_t reserved0; //!< [0x008-0x00b] Reserved for future use
|
||||
uint8_t readSampleClkSrc; //!< [0x00c-0x00c] Read Sample Clock Source, valid value: 0/1/3
|
||||
uint8_t csHoldTime; //!< [0x00d-0x00d] CS hold time, default value: 3
|
||||
uint8_t csSetupTime; //!< [0x00e-0x00e] CS setup time, default value: 3
|
||||
uint8_t columnAddressWidth; //!< [0x00f-0x00f] Column Address with, for HyperBus protocol, it is fixed to 3, For
|
||||
//! Serial NAND, need to refer to datasheet
|
||||
uint8_t deviceModeCfgEnable; //!< [0x010-0x010] Device Mode Configure enable flag, 1 - Enable, 0 - Disable
|
||||
uint8_t deviceModeType; //!< [0x011-0x011] Specify the configuration command type:Quad Enable, DPI/QPI/OPI switch,
|
||||
//! Generic configuration, etc.
|
||||
uint16_t waitTimeCfgCommands; //!< [0x012-0x013] Wait time for all configuration commands, unit: 100us, Used for
|
||||
//! DPI/QPI/OPI switch or reset command
|
||||
flexspi_lut_seq_t deviceModeSeq; //!< [0x014-0x017] Device mode sequence info, [7:0] - LUT sequence id, [15:8] - LUt
|
||||
//! sequence number, [31:16] Reserved
|
||||
uint32_t deviceModeArg; //!< [0x018-0x01b] Argument/Parameter for device configuration
|
||||
uint8_t configCmdEnable; //!< [0x01c-0x01c] Configure command Enable Flag, 1 - Enable, 0 - Disable
|
||||
uint8_t configModeType[3]; //!< [0x01d-0x01f] Configure Mode Type, similar as deviceModeTpe
|
||||
flexspi_lut_seq_t
|
||||
configCmdSeqs[3]; //!< [0x020-0x02b] Sequence info for Device Configuration command, similar as deviceModeSeq
|
||||
uint32_t reserved1; //!< [0x02c-0x02f] Reserved for future use
|
||||
uint32_t configCmdArgs[3]; //!< [0x030-0x03b] Arguments/Parameters for device Configuration commands
|
||||
uint32_t reserved2; //!< [0x03c-0x03f] Reserved for future use
|
||||
uint32_t controllerMiscOption; //!< [0x040-0x043] Controller Misc Options, see Misc feature bit definitions for more
|
||||
//! details
|
||||
uint8_t deviceType; //!< [0x044-0x044] Device Type: See Flash Type Definition for more details
|
||||
uint8_t sflashPadType; //!< [0x045-0x045] Serial Flash Pad Type: 1 - Single, 2 - Dual, 4 - Quad, 8 - Octal
|
||||
uint8_t serialClkFreq; //!< [0x046-0x046] Serial Flash Frequency, device specific definitions, See System Boot
|
||||
//! Chapter for more details
|
||||
uint8_t lutCustomSeqEnable; //!< [0x047-0x047] LUT customization Enable, it is required if the program/erase cannot
|
||||
//! be done using 1 LUT sequence, currently, only applicable to HyperFLASH
|
||||
uint32_t reserved3[2]; //!< [0x048-0x04f] Reserved for future use
|
||||
uint32_t sflashA1Size; //!< [0x050-0x053] Size of Flash connected to A1
|
||||
uint32_t sflashA2Size; //!< [0x054-0x057] Size of Flash connected to A2
|
||||
uint32_t sflashB1Size; //!< [0x058-0x05b] Size of Flash connected to B1
|
||||
uint32_t sflashB2Size; //!< [0x05c-0x05f] Size of Flash connected to B2
|
||||
uint32_t csPadSettingOverride; //!< [0x060-0x063] CS pad setting override value
|
||||
uint32_t sclkPadSettingOverride; //!< [0x064-0x067] SCK pad setting override value
|
||||
uint32_t dataPadSettingOverride; //!< [0x068-0x06b] data pad setting override value
|
||||
uint32_t dqsPadSettingOverride; //!< [0x06c-0x06f] DQS pad setting override value
|
||||
uint32_t timeoutInMs; //!< [0x070-0x073] Timeout threshold for read status command
|
||||
uint32_t commandInterval; //!< [0x074-0x077] CS deselect interval between two commands
|
||||
uint16_t dataValidTime[2]; //!< [0x078-0x07b] CLK edge to data valid time for PORT A and PORT B, in terms of 0.1ns
|
||||
uint16_t busyOffset; //!< [0x07c-0x07d] Busy offset, valid value: 0-31
|
||||
uint16_t busyBitPolarity; //!< [0x07e-0x07f] Busy flag polarity, 0 - busy flag is 1 when flash device is busy, 1 -
|
||||
//! busy flag is 0 when flash device is busy
|
||||
uint32_t lookupTable[64]; //!< [0x080-0x17f] Lookup table holds Flash command sequences
|
||||
flexspi_lut_seq_t lutCustomSeq[12]; //!< [0x180-0x1af] Customizable LUT Sequences
|
||||
uint32_t reserved4[4]; //!< [0x1b0-0x1bf] Reserved for future use
|
||||
} flexspi_mem_config_t;
|
||||
|
||||
/* */
|
||||
#define NOR_CMD_INDEX_READ CMD_INDEX_READ //!< 0
|
||||
#define NOR_CMD_INDEX_READSTATUS CMD_INDEX_READSTATUS //!< 1
|
||||
#define NOR_CMD_INDEX_WRITEENABLE CMD_INDEX_WRITEENABLE //!< 2
|
||||
#define NOR_CMD_INDEX_ERASESECTOR 3 //!< 3
|
||||
#define NOR_CMD_INDEX_PAGEPROGRAM CMD_INDEX_WRITE //!< 4
|
||||
#define NOR_CMD_INDEX_CHIPERASE 5 //!< 5
|
||||
#define NOR_CMD_INDEX_DUMMY 6 //!< 6
|
||||
#define NOR_CMD_INDEX_ERASEBLOCK 7 //!< 7
|
||||
|
||||
#define NOR_CMD_LUT_SEQ_IDX_READ CMD_LUT_SEQ_IDX_READ //!< 0 READ LUT sequence id in lookupTable stored in config block
|
||||
#define NOR_CMD_LUT_SEQ_IDX_READSTATUS \
|
||||
CMD_LUT_SEQ_IDX_READSTATUS //!< 1 Read Status LUT sequence id in lookupTable stored in config block
|
||||
#define NOR_CMD_LUT_SEQ_IDX_READSTATUS_XPI \
|
||||
2 //!< 2 Read status DPI/QPI/OPI sequence id in lookupTable stored in config block
|
||||
#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE \
|
||||
CMD_LUT_SEQ_IDX_WRITEENABLE //!< 3 Write Enable sequence id in lookupTable stored in config block
|
||||
#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE_XPI \
|
||||
4 //!< 4 Write Enable DPI/QPI/OPI sequence id in lookupTable stored in config block
|
||||
#define NOR_CMD_LUT_SEQ_IDX_ERASESECTOR 5 //!< 5 Erase Sector sequence id in lookupTable stored in config block
|
||||
#define NOR_CMD_LUT_SEQ_IDX_ERASEBLOCK 8 //!< 8 Erase Block sequence id in lookupTable stored in config block
|
||||
#define NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM \
|
||||
CMD_LUT_SEQ_IDX_WRITE //!< 9 Program sequence id in lookupTable stored in config block
|
||||
#define NOR_CMD_LUT_SEQ_IDX_CHIPERASE 11 //!< 11 Chip Erase sequence in lookupTable id stored in config block
|
||||
#define NOR_CMD_LUT_SEQ_IDX_READ_SFDP 13 //!< 13 Read SFDP sequence in lookupTable id stored in config block
|
||||
#define NOR_CMD_LUT_SEQ_IDX_RESTORE_NOCMD \
|
||||
14 //!< 14 Restore 0-4-4/0-8-8 mode sequence id in lookupTable stored in config block
|
||||
#define NOR_CMD_LUT_SEQ_IDX_EXIT_NOCMD \
|
||||
15 //!< 15 Exit 0-4-4/0-8-8 mode sequence id in lookupTable stored in config blobk
|
||||
|
||||
/*
|
||||
* Serial NOR configuration block
|
||||
*/
|
||||
typedef struct _flexspi_nor_config
|
||||
{
|
||||
flexspi_mem_config_t memConfig; //!< Common memory configuration info via FlexSPI
|
||||
uint32_t pageSize; //!< Page size of Serial NOR
|
||||
uint32_t sectorSize; //!< Sector size of Serial NOR
|
||||
uint8_t ipcmdSerialClkFreq; //!< Clock frequency for IP command
|
||||
uint8_t isUniformBlockSize; //!< Sector/Block size is the same
|
||||
uint8_t reserved0[2]; //!< Reserved for future use
|
||||
uint8_t serialNorType; //!< Serial NOR Flash type: 0/1/2/3
|
||||
uint8_t needExitNoCmdMode; //!< Need to exit NoCmd mode before other IP command
|
||||
uint8_t halfClkForNonReadCmd; //!< Half the Serial Clock for non-read command: true/false
|
||||
uint8_t needRestoreNoCmdMode; //!< Need to Restore NoCmd mode after IP command execution
|
||||
uint32_t blockSize; //!< Block size
|
||||
uint32_t reserve2[11]; //!< Reserved for future use
|
||||
} flexspi_nor_config_t;
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
#endif /* __EVKMIMXRT1015_FLEXSPI_NOR_CONFIG__ */
|
||||
+473
@@ -0,0 +1,473 @@
|
||||
<?xml version="1.0" encoding= "UTF-8" ?>
|
||||
<configuration name="MIMXRT1015-EVK" xsi:schemaLocation="http://mcuxpresso.nxp.com/XSD/mex_configuration_17 http://mcuxpresso.nxp.com/XSD/mex_configuration_17.xsd" uuid="4be4468a-3124-4ac9-9d4f-05d5f8ad6399" version="17" xmlns="http://mcuxpresso.nxp.com/XSD/mex_configuration_17" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
|
||||
<common>
|
||||
<processor>MIMXRT1015xxxxx</processor>
|
||||
<package>MIMXRT1015DAF5A</package>
|
||||
<board>MIMXRT1015-EVK</board>
|
||||
<board_revision>B</board_revision>
|
||||
<mcu_data>ksdk2_0</mcu_data>
|
||||
<cores selected="core0">
|
||||
<core name="Cortex-M7F" id="core0" description="M7 core"/>
|
||||
</cores>
|
||||
<description></description>
|
||||
</common>
|
||||
<preferences>
|
||||
<validate_boot_init_only>true</validate_boot_init_only>
|
||||
<generate_code_modified_registers_only>false</generate_code_modified_registers_only>
|
||||
<update_include_paths>true</update_include_paths>
|
||||
<generate_registers_defines>false</generate_registers_defines>
|
||||
</preferences>
|
||||
<tools>
|
||||
<pins name="Pins" version="17.0" enabled="true" update_project_code="true">
|
||||
<generated_project_files>
|
||||
<file path="board/pin_mux.c" update_enabled="true"/>
|
||||
<file path="board/pin_mux.h" update_enabled="true"/>
|
||||
</generated_project_files>
|
||||
<pins_profile>
|
||||
<processor_version>24.12.10</processor_version>
|
||||
<pin_labels>
|
||||
<pin_label pin_num="21" pin_signal="GPIO_SD_B1_01" label="GPIO SD_B1_01" identifier="USER_LED"/>
|
||||
</pin_labels>
|
||||
<external_user_signals>
|
||||
<properties/>
|
||||
</external_user_signals>
|
||||
<power_domains>
|
||||
<power_domain name="NVCC_GPIO" value="3.3"/>
|
||||
</power_domains>
|
||||
</pins_profile>
|
||||
<functions_list>
|
||||
<function name="BOARD_InitPins">
|
||||
<description>Configures pin routing and optionally pin electrical features.</description>
|
||||
<options>
|
||||
<callFromInitBoot>true</callFromInitBoot>
|
||||
<coreID>core0</coreID>
|
||||
<enableClock>true</enableClock>
|
||||
</options>
|
||||
<dependencies>
|
||||
<dependency resourceType="Peripheral" resourceId="GPIO2" description="Peripheral GPIO2 signals are routed in the Pins Tool, but the peripheral is not initialized in the Peripherals Tool." problem_level="1" source="Pins:BOARD_InitPins">
|
||||
<feature name="initialized" evaluation="equal">
|
||||
<data>true</data>
|
||||
</feature>
|
||||
</dependency>
|
||||
<dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitPins">
|
||||
<feature name="enabled" evaluation="equal" configuration="core0">
|
||||
<data>true</data>
|
||||
</feature>
|
||||
</dependency>
|
||||
<dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Pins initialization requires the IOMUXC Driver in the project." problem_level="2" source="Pins:BOARD_InitPins">
|
||||
<feature name="enabled" evaluation="equal" configuration="core0">
|
||||
<data>true</data>
|
||||
</feature>
|
||||
</dependency>
|
||||
<dependency resourceType="SWComponent" resourceId="platform.drivers.igpio" description="Pins initialization requires the IGPIO Driver in the project." problem_level="2" source="Pins:BOARD_InitPins">
|
||||
<feature name="enabled" evaluation="equal" configuration="core0">
|
||||
<data>true</data>
|
||||
</feature>
|
||||
</dependency>
|
||||
</dependencies>
|
||||
<pins>
|
||||
<pin peripheral="GPIO2" signal="gpio_io, 09" pin_num="1" pin_signal="GPIO_EMC_09">
|
||||
<pin_features>
|
||||
<pin_feature name="direction" value="INPUT"/>
|
||||
<pin_feature name="pull_keeper_select" value="Pull"/>
|
||||
<pin_feature name="pull_up_down_config" value="Pull_Up_47K_Ohm"/>
|
||||
</pin_features>
|
||||
</pin>
|
||||
<pin peripheral="GPIO3" signal="gpio_io, 21" pin_num="21" pin_signal="GPIO_SD_B1_01">
|
||||
<pin_features>
|
||||
<pin_feature name="direction" value="OUTPUT"/>
|
||||
</pin_features>
|
||||
</pin>
|
||||
</pins>
|
||||
</function>
|
||||
<function name="BOARD_InitQSPIPins">
|
||||
<description>Configures pin routing and optionally pin electrical features.</description>
|
||||
<options>
|
||||
<callFromInitBoot>false</callFromInitBoot>
|
||||
<coreID>core0</coreID>
|
||||
<enableClock>true</enableClock>
|
||||
</options>
|
||||
<dependencies>
|
||||
<dependency resourceType="Peripheral" resourceId="FLEXSPI" description="Peripheral FLEXSPI signals are routed in the Pins Tool, but the peripheral is not initialized in the Peripherals Tool." problem_level="1" source="Pins:BOARD_InitQSPIPins">
|
||||
<feature name="initialized" evaluation="equal">
|
||||
<data>true</data>
|
||||
</feature>
|
||||
</dependency>
|
||||
<dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitQSPIPins">
|
||||
<feature name="enabled" evaluation="equal" configuration="core0">
|
||||
<data>true</data>
|
||||
</feature>
|
||||
</dependency>
|
||||
<dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Pins initialization requires the IOMUXC Driver in the project." problem_level="2" source="Pins:BOARD_InitQSPIPins">
|
||||
<feature name="enabled" evaluation="equal" configuration="core0">
|
||||
<data>true</data>
|
||||
</feature>
|
||||
</dependency>
|
||||
</dependencies>
|
||||
<pins>
|
||||
<pin peripheral="FLEXSPI" signal="FLEXSPI_A_SCLK" pin_num="12" pin_signal="GPIO_SD_B1_07"/>
|
||||
<pin peripheral="FLEXSPI" signal="FLEXSPI_A_DATA0" pin_num="11" pin_signal="GPIO_SD_B1_08"/>
|
||||
<pin peripheral="FLEXSPI" signal="FLEXSPI_A_DATA1" pin_num="9" pin_signal="GPIO_SD_B1_10"/>
|
||||
<pin peripheral="FLEXSPI" signal="FLEXSPI_A_DATA2" pin_num="10" pin_signal="GPIO_SD_B1_09"/>
|
||||
<pin peripheral="FLEXSPI" signal="FLEXSPI_A_DATA3" pin_num="13" pin_signal="GPIO_SD_B1_06"/>
|
||||
<pin peripheral="FLEXSPI" signal="FLEXSPI_A_SS0_B" pin_num="8" pin_signal="GPIO_SD_B1_11"/>
|
||||
</pins>
|
||||
</function>
|
||||
<function name="BOARD_InitDEBUG_UARTPins">
|
||||
<description>Configures pin routing and optionally pin electrical features.</description>
|
||||
<options>
|
||||
<callFromInitBoot>true</callFromInitBoot>
|
||||
<coreID>core0</coreID>
|
||||
<enableClock>true</enableClock>
|
||||
</options>
|
||||
<dependencies>
|
||||
<dependency resourceType="Peripheral" resourceId="LPUART1" description="Peripheral LPUART1 signals are routed in the Pins Tool, but the peripheral is not initialized in the Peripherals Tool." problem_level="1" source="Pins:BOARD_InitDEBUG_UARTPins">
|
||||
<feature name="initialized" evaluation="equal">
|
||||
<data>true</data>
|
||||
</feature>
|
||||
</dependency>
|
||||
<dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitDEBUG_UARTPins">
|
||||
<feature name="enabled" evaluation="equal" configuration="core0">
|
||||
<data>true</data>
|
||||
</feature>
|
||||
</dependency>
|
||||
<dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Pins initialization requires the IOMUXC Driver in the project." problem_level="2" source="Pins:BOARD_InitDEBUG_UARTPins">
|
||||
<feature name="enabled" evaluation="equal" configuration="core0">
|
||||
<data>true</data>
|
||||
</feature>
|
||||
</dependency>
|
||||
</dependencies>
|
||||
<pins>
|
||||
<pin peripheral="LPUART1" signal="RX" pin_num="68" pin_signal="GPIO_AD_B0_07">
|
||||
<pin_features>
|
||||
<pin_feature name="slew_rate" value="Slow"/>
|
||||
</pin_features>
|
||||
</pin>
|
||||
<pin peripheral="LPUART1" signal="TX" pin_num="72" pin_signal="GPIO_AD_B0_06">
|
||||
<pin_features>
|
||||
<pin_feature name="slew_rate" value="Slow"/>
|
||||
</pin_features>
|
||||
</pin>
|
||||
</pins>
|
||||
</function>
|
||||
</functions_list>
|
||||
</pins>
|
||||
<clocks name="Clocks" version="15.0" enabled="true" update_project_code="true">
|
||||
<generated_project_files>
|
||||
<file path="board/clock_config.c" update_enabled="true"/>
|
||||
<file path="board/clock_config.h" update_enabled="true"/>
|
||||
</generated_project_files>
|
||||
<clocks_profile>
|
||||
<processor_version>24.12.10</processor_version>
|
||||
</clocks_profile>
|
||||
<clock_configurations>
|
||||
<clock_configuration name="BOARD_BootClockRUN" id_prefix="" prefix_user_defined="false">
|
||||
<description></description>
|
||||
<options/>
|
||||
<dependencies>
|
||||
<dependency resourceType="PinSignal" resourceId="XTALOSC24M.rtc_xtali" description="'RTC_XTALI' (Pins tool id: XTALOSC24M.rtc_xtali, Clocks tool id: XTALOSC24M.RTC_XTALI) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockRUN">
|
||||
<feature name="routed" evaluation="">
|
||||
<data>true</data>
|
||||
</feature>
|
||||
</dependency>
|
||||
<dependency resourceType="PinSignal" resourceId="XTALOSC24M.rtc_xtali" description="'RTC_XTALI' (Pins tool id: XTALOSC24M.rtc_xtali, Clocks tool id: XTALOSC24M.RTC_XTALI) needs to have 'INPUT' direction" problem_level="1" source="Clocks:BOARD_BootClockRUN">
|
||||
<feature name="direction" evaluation="">
|
||||
<data>INPUT</data>
|
||||
</feature>
|
||||
</dependency>
|
||||
<dependency resourceType="PinSignal" resourceId="XTALOSC24M.rtc_xtalo" description="'RTC_XTALO' (Pins tool id: XTALOSC24M.rtc_xtalo, Clocks tool id: XTALOSC24M.RTC_XTALO) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockRUN">
|
||||
<feature name="routed" evaluation="">
|
||||
<data>true</data>
|
||||
</feature>
|
||||
</dependency>
|
||||
<dependency resourceType="PinSignal" resourceId="XTALOSC24M.rtc_xtalo" description="'RTC_XTALO' (Pins tool id: XTALOSC24M.rtc_xtalo, Clocks tool id: XTALOSC24M.RTC_XTALO) needs to have 'OUTPUT' direction" problem_level="1" source="Clocks:BOARD_BootClockRUN">
|
||||
<feature name="direction" evaluation="">
|
||||
<data>OUTPUT</data>
|
||||
</feature>
|
||||
</dependency>
|
||||
<dependency resourceType="PinSignal" resourceId="XTALOSC24M.xtali" description="'XTALI' (Pins tool id: XTALOSC24M.xtali, Clocks tool id: XTALOSC24M.XTALI) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockRUN">
|
||||
<feature name="routed" evaluation="">
|
||||
<data>true</data>
|
||||
</feature>
|
||||
</dependency>
|
||||
<dependency resourceType="PinSignal" resourceId="XTALOSC24M.xtali" description="'XTALI' (Pins tool id: XTALOSC24M.xtali, Clocks tool id: XTALOSC24M.XTALI) needs to have 'INPUT' direction" problem_level="1" source="Clocks:BOARD_BootClockRUN">
|
||||
<feature name="direction" evaluation="">
|
||||
<data>INPUT</data>
|
||||
</feature>
|
||||
</dependency>
|
||||
<dependency resourceType="PinSignal" resourceId="XTALOSC24M.xtalo" description="'XTALO' (Pins tool id: XTALOSC24M.xtalo, Clocks tool id: XTALOSC24M.XTALO) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockRUN">
|
||||
<feature name="routed" evaluation="">
|
||||
<data>true</data>
|
||||
</feature>
|
||||
</dependency>
|
||||
<dependency resourceType="PinSignal" resourceId="XTALOSC24M.xtalo" description="'XTALO' (Pins tool id: XTALOSC24M.xtalo, Clocks tool id: XTALOSC24M.XTALO) needs to have 'OUTPUT' direction" problem_level="1" source="Clocks:BOARD_BootClockRUN">
|
||||
<feature name="direction" evaluation="">
|
||||
<data>OUTPUT</data>
|
||||
</feature>
|
||||
</dependency>
|
||||
<dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Clocks initialization requires the COMMON Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockRUN">
|
||||
<feature name="enabled" evaluation="equal" configuration="core0">
|
||||
<data>true</data>
|
||||
</feature>
|
||||
</dependency>
|
||||
<dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Clocks initialization requires the IOMUXC Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockRUN">
|
||||
<feature name="enabled" evaluation="equal" configuration="core0">
|
||||
<data>true</data>
|
||||
</feature>
|
||||
</dependency>
|
||||
</dependencies>
|
||||
<clock_sources>
|
||||
<clock_source id="XTALOSC24M.RTC_OSC.outFreq" value="32.768 kHz" locked="false" enabled="true"/>
|
||||
</clock_sources>
|
||||
<clock_outputs>
|
||||
<clock_output id="AHB_CLK_ROOT.outFreq" value="500 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="CKIL_SYNC_CLK_ROOT.outFreq" value="32.768 kHz" locked="false" accuracy=""/>
|
||||
<clock_output id="CLK_1M.outFreq" value="1 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="CLK_24M.outFreq" value="24 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="ENET_500M_REF_CLK.outFreq" value="500 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="FLEXIO1_CLK_ROOT.outFreq" value="30 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="FLEXSPI_CLK_ROOT.outFreq" value="2160/11 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="GPT1_ipg_clk_highfreq.outFreq" value="62.5 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="GPT2_ipg_clk_highfreq.outFreq" value="62.5 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="IPG_CLK_ROOT.outFreq" value="125 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="LPI2C_CLK_ROOT.outFreq" value="60 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="LPSPI_CLK_ROOT.outFreq" value="105.6 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="MQS_MCLK.outFreq" value="1080/17 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="PERCLK_CLK_ROOT.outFreq" value="62.5 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="SAI1_CLK_ROOT.outFreq" value="1080/17 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="SAI1_MCLK1.outFreq" value="1080/17 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="SAI1_MCLK2.outFreq" value="1080/17 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="SAI1_MCLK3.outFreq" value="30 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="SAI2_CLK_ROOT.outFreq" value="1080/17 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="SAI2_MCLK1.outFreq" value="1080/17 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="SAI2_MCLK3.outFreq" value="30 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="SAI3_CLK_ROOT.outFreq" value="1080/17 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="SAI3_MCLK1.outFreq" value="1080/17 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="SAI3_MCLK3.outFreq" value="30 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="SPDIF0_CLK_ROOT.outFreq" value="30 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="TRACE_CLK_ROOT.outFreq" value="352/3 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="UART_CLK_ROOT.outFreq" value="80 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="USBPHY1_CLK.outFreq" value="480 MHz" locked="false" accuracy=""/>
|
||||
</clock_outputs>
|
||||
<clock_settings>
|
||||
<setting id="CCM.AHB_PODF.scale" value="1" locked="true"/>
|
||||
<setting id="CCM.ARM_PODF.scale" value="1" locked="true"/>
|
||||
<setting id="CCM.CLKO2_SEL.sel" value="CCM.LPI2C_CLK_ROOT" locked="false"/>
|
||||
<setting id="CCM.FLEXSPI_PODF.scale" value="2" locked="true"/>
|
||||
<setting id="CCM.FLEXSPI_SEL.sel" value="CCM_ANALOG.PLL3_PFD0_CLK" locked="false"/>
|
||||
<setting id="CCM.IPG_PODF.scale" value="4" locked="false"/>
|
||||
<setting id="CCM.LPSPI_PODF.scale" value="5" locked="true"/>
|
||||
<setting id="CCM.PERCLK_PODF.scale" value="2" locked="true"/>
|
||||
<setting id="CCM.PRE_PERIPH_CLK_SEL.sel" value="CCM.ARM_PODF" locked="false"/>
|
||||
<setting id="CCM.SEMC_PODF.scale" value="2" locked="false"/>
|
||||
<setting id="CCM.TRACE_PODF.scale" value="3" locked="true"/>
|
||||
<setting id="CCM_ANALOG.PLL2.denom" value="1" locked="true"/>
|
||||
<setting id="CCM_ANALOG.PLL2.num" value="0" locked="true"/>
|
||||
<setting id="CCM_ANALOG.PLL2_BYPASS.sel" value="CCM_ANALOG.PLL2_OUT_CLK" locked="false"/>
|
||||
<setting id="CCM_ANALOG.PLL2_PFD0_BYPASS.sel" value="CCM_ANALOG.PLL2_PFD0" locked="false"/>
|
||||
<setting id="CCM_ANALOG.PLL2_PFD1_BYPASS.sel" value="CCM_ANALOG.PLL2_PFD1" locked="false"/>
|
||||
<setting id="CCM_ANALOG.PLL2_PFD2_BYPASS.sel" value="CCM_ANALOG.PLL2_PFD2" locked="false"/>
|
||||
<setting id="CCM_ANALOG.PLL2_PFD2_DIV.scale" value="18" locked="true"/>
|
||||
<setting id="CCM_ANALOG.PLL2_PFD2_MUL.scale" value="18" locked="true"/>
|
||||
<setting id="CCM_ANALOG.PLL2_PFD3_BYPASS.sel" value="CCM_ANALOG.PLL2_PFD3" locked="false"/>
|
||||
<setting id="CCM_ANALOG.PLL2_PFD3_DIV.scale" value="18" locked="true"/>
|
||||
<setting id="CCM_ANALOG.PLL2_PFD3_MUL.scale" value="18" locked="true"/>
|
||||
<setting id="CCM_ANALOG.PLL3_BYPASS.sel" value="CCM_ANALOG.PLL3" locked="false"/>
|
||||
<setting id="CCM_ANALOG.PLL3_PFD0_BYPASS.sel" value="CCM_ANALOG.PLL3_PFD0" locked="false"/>
|
||||
<setting id="CCM_ANALOG.PLL3_PFD0_DIV.scale" value="22" locked="true"/>
|
||||
<setting id="CCM_ANALOG.PLL3_PFD0_MUL.scale" value="18" locked="true"/>
|
||||
<setting id="CCM_ANALOG.PLL3_PFD1_BYPASS.sel" value="CCM_ANALOG.PLL3_PFD1" locked="false"/>
|
||||
<setting id="CCM_ANALOG.PLL3_PFD2_BYPASS.sel" value="CCM_ANALOG.PLL3_PFD2" locked="false"/>
|
||||
<setting id="CCM_ANALOG.PLL3_PFD3_BYPASS.sel" value="CCM_ANALOG.PLL3_PFD3" locked="false"/>
|
||||
<setting id="CCM_ANALOG.PLL3_PFD3_DIV.scale" value="18" locked="true"/>
|
||||
<setting id="CCM_ANALOG.PLL3_PFD3_MUL.scale" value="18" locked="true"/>
|
||||
<setting id="CCM_ANALOG.PLL4.denom" value="50" locked="false"/>
|
||||
<setting id="CCM_ANALOG.PLL4.div" value="47" locked="false"/>
|
||||
<setting id="CCM_ANALOG.PLL6_BYPASS.sel" value="CCM_ANALOG.PLL6" locked="false"/>
|
||||
<setting id="CCM_ANALOG_PLL_USB1_EN_USB_CLKS_CFG" value="Enabled" locked="false"/>
|
||||
<setting id="CCM_ANALOG_PLL_USB1_EN_USB_CLKS_OUT_CFG" value="Enabled" locked="false"/>
|
||||
<setting id="CCM_ANALOG_PLL_USB1_POWER_CFG" value="Yes" locked="false"/>
|
||||
</clock_settings>
|
||||
<called_from_default_init>true</called_from_default_init>
|
||||
</clock_configuration>
|
||||
</clock_configurations>
|
||||
</clocks>
|
||||
<dcdx name="DCDx" version="3.0" enabled="false" update_project_code="true">
|
||||
<generated_project_files/>
|
||||
<dcdx_profile>
|
||||
<processor_version>N/A</processor_version>
|
||||
</dcdx_profile>
|
||||
<dcdx_configurations/>
|
||||
</dcdx>
|
||||
<periphs name="Peripherals" version="12.0" enabled="false" update_project_code="true">
|
||||
<generated_project_files/>
|
||||
<peripherals_profile>
|
||||
<processor_version>13.0.2</processor_version>
|
||||
</peripherals_profile>
|
||||
<functional_groups>
|
||||
<functional_group name="BOARD_InitPeripherals" uuid="57fc488c-a9f7-4a03-8ab3-5d2a3fd16a50" called_from_default_init="true" id_prefix="" core="core0">
|
||||
<description></description>
|
||||
<options/>
|
||||
<dependencies/>
|
||||
<instances>
|
||||
<instance name="DEBUG_UART" uuid="600d7aee-5a2d-4373-9763-ce007b981c15" type="lpuart" type_id="lpuart_bebe3e12b6ec22bbd14199038f2bf459" mode="polling" peripheral="LPUART1" enabled="false" comment="" custom_name_enabled="true" editing_lock="false">
|
||||
<config_set name="lpuartConfig_t" quick_selection="QuickSelection1">
|
||||
<struct name="lpuartConfig">
|
||||
<setting name="clockSource" value="LpuartClock"/>
|
||||
<setting name="lpuartSrcClkFreq" value="ClocksTool_DefaultInit"/>
|
||||
<setting name="baudRate_Bps" value="115200"/>
|
||||
<setting name="parityMode" value="kLPUART_ParityDisabled"/>
|
||||
<setting name="dataBitsCount" value="kLPUART_EightDataBits"/>
|
||||
<setting name="isMsb" value="false"/>
|
||||
<setting name="stopBitCount" value="kLPUART_OneStopBit"/>
|
||||
<setting name="txFifoWatermark" value="0"/>
|
||||
<setting name="rxFifoWatermark" value="1"/>
|
||||
<setting name="enableRxRTS" value="false"/>
|
||||
<setting name="enableTxCTS" value="false"/>
|
||||
<setting name="txCtsSource" value="kLPUART_CtsSourcePin"/>
|
||||
<setting name="txCtsConfig" value="kLPUART_CtsSampleAtStart"/>
|
||||
<setting name="rxIdleType" value="kLPUART_IdleTypeStartBit"/>
|
||||
<setting name="rxIdleConfig" value="kLPUART_IdleCharacter1"/>
|
||||
<setting name="enableTx" value="true"/>
|
||||
<setting name="enableRx" value="true"/>
|
||||
</struct>
|
||||
</config_set>
|
||||
</instance>
|
||||
<instance name="COMBO_SENSOR" uuid="96f9e552-25e5-434a-9454-5cf9e614733d" type="lpi2c" type_id="lpi2c_db68d4f4f06a22e25ab51fe9bd6db4d2" mode="master" peripheral="LPI2C1" enabled="false" comment="" custom_name_enabled="true" editing_lock="false">
|
||||
<config_set name="main" quick_selection="qs_interrupt">
|
||||
<setting name="clockSource" value="Lpi2cClock"/>
|
||||
<setting name="clockSourceFreq" value="ClocksTool_DefaultInit"/>
|
||||
<struct name="interrupt">
|
||||
<setting name="IRQn" value="LPI2C1_IRQn"/>
|
||||
<setting name="enable_interrrupt" value="enabled"/>
|
||||
<setting name="enable_priority" value="false"/>
|
||||
<setting name="priority" value="0"/>
|
||||
<setting name="enable_custom_name" value="false"/>
|
||||
</struct>
|
||||
</config_set>
|
||||
<config_set name="master" quick_selection="qs_master_transfer">
|
||||
<setting name="mode" value="transfer"/>
|
||||
<struct name="config">
|
||||
<setting name="enableMaster" value="true"/>
|
||||
<setting name="enableDoze" value="true"/>
|
||||
<setting name="debugEnable" value="false"/>
|
||||
<setting name="ignoreAck" value="false"/>
|
||||
<setting name="pinConfig" value="kLPI2C_2PinOpenDrain"/>
|
||||
<setting name="baudRate_Hz" value="100000"/>
|
||||
<setting name="busIdleTimeout_ns" value="0"/>
|
||||
<setting name="pinLowTimeout_ns" value="0"/>
|
||||
<setting name="sdaGlitchFilterWidth_ns" value="0"/>
|
||||
<setting name="sclGlitchFilterWidth_ns" value="0"/>
|
||||
<struct name="hostRequest">
|
||||
<setting name="enable" value="false"/>
|
||||
<setting name="source" value="kLPI2C_HostRequestExternalPin"/>
|
||||
<setting name="polarity" value="kLPI2C_HostRequestPinActiveHigh"/>
|
||||
</struct>
|
||||
<set name="edmaRequestSources">
|
||||
<selected/>
|
||||
</set>
|
||||
</struct>
|
||||
<struct name="transfer">
|
||||
<setting name="blocking" value="false"/>
|
||||
<setting name="enable_custom_handle" value="false"/>
|
||||
<struct name="callback">
|
||||
<setting name="name" value=""/>
|
||||
<setting name="userData" value=""/>
|
||||
</struct>
|
||||
<set name="flags">
|
||||
<selected/>
|
||||
</set>
|
||||
<setting name="slaveAddress" value="0"/>
|
||||
<setting name="direction" value="kLPI2C_Write"/>
|
||||
<setting name="subaddress" value="0"/>
|
||||
<setting name="subaddressSize" value="1"/>
|
||||
<setting name="blocking_buffer" value="false"/>
|
||||
<setting name="enable_custom_buffer" value="false"/>
|
||||
<setting name="dataSize" value="1"/>
|
||||
</struct>
|
||||
</config_set>
|
||||
</instance>
|
||||
<instance name="USER_LED" uuid="5592aac0-ced9-4284-88a8-bbeb5083a92f" type="igpio" type_id="igpio_b1c1fa279aa7069dca167502b8589cb7" mode="GPIO" peripheral="GPIO3" enabled="false" comment="" custom_name_enabled="true" editing_lock="false">
|
||||
<config_set name="fsl_gpio">
|
||||
<setting name="enable_irq_comb_0_15" value="false"/>
|
||||
<struct name="gpio_interrupt_comb_0_15">
|
||||
<setting name="IRQn" value="GPIO3_Combined_0_15_IRQn"/>
|
||||
<setting name="enable_interrrupt" value="enabled"/>
|
||||
<setting name="enable_priority" value="false"/>
|
||||
<setting name="priority" value="0"/>
|
||||
<setting name="enable_custom_name" value="false"/>
|
||||
</struct>
|
||||
<setting name="enable_irq_comb_16_31" value="false"/>
|
||||
<struct name="gpio_interrupt_comb_16_31">
|
||||
<setting name="IRQn" value="GPIO3_Combined_16_31_IRQn"/>
|
||||
<setting name="enable_interrrupt" value="enabled"/>
|
||||
<setting name="enable_priority" value="false"/>
|
||||
<setting name="priority" value="0"/>
|
||||
<setting name="enable_custom_name" value="false"/>
|
||||
</struct>
|
||||
</config_set>
|
||||
</instance>
|
||||
<instance name="USER_BUTTON" uuid="e7774953-3606-41b8-8b72-6e09025369e0" type="igpio" type_id="igpio_b1c1fa279aa7069dca167502b8589cb7" mode="GPIO" peripheral="GPIO2" enabled="false" comment="" custom_name_enabled="true" editing_lock="false">
|
||||
<config_set name="fsl_gpio">
|
||||
<setting name="enable_irq_comb_0_15" value="false"/>
|
||||
<struct name="gpio_interrupt_comb_0_15">
|
||||
<setting name="IRQn" value="GPIO2_Combined_0_15_IRQn"/>
|
||||
<setting name="enable_interrrupt" value="enabled"/>
|
||||
<setting name="enable_priority" value="false"/>
|
||||
<setting name="priority" value="0"/>
|
||||
<setting name="enable_custom_name" value="false"/>
|
||||
</struct>
|
||||
<setting name="enable_irq_comb_16_31" value="false"/>
|
||||
<struct name="gpio_interrupt_comb_16_31">
|
||||
<setting name="IRQn" value="GPIO2_Combined_16_31_IRQn"/>
|
||||
<setting name="enable_interrrupt" value="enabled"/>
|
||||
<setting name="enable_priority" value="false"/>
|
||||
<setting name="priority" value="0"/>
|
||||
<setting name="enable_custom_name" value="false"/>
|
||||
</struct>
|
||||
</config_set>
|
||||
</instance>
|
||||
<instance name="NVIC" uuid="0329fbca-00e5-4ec4-9f79-3cb65a7b267a" type="nvic" type_id="nvic_57b5eef3774cc60acaede6f5b8bddc67" mode="general" peripheral="NVIC" enabled="true" comment="" custom_name_enabled="false" editing_lock="false">
|
||||
<config_set name="nvic">
|
||||
<array name="interrupt_table"/>
|
||||
<array name="interrupts"/>
|
||||
</config_set>
|
||||
</instance>
|
||||
</instances>
|
||||
</functional_group>
|
||||
</functional_groups>
|
||||
<components>
|
||||
<component name="system" uuid="59cf1b09-8396-4bf9-bed6-03d5457c292f" type_id="system_54b53072540eeeb8f8e9343e71f28176">
|
||||
<config_set_global name="global_system_definitions">
|
||||
<setting name="user_definitions" value=""/>
|
||||
<setting name="user_includes" value=""/>
|
||||
</config_set_global>
|
||||
</component>
|
||||
<component name="msg" uuid="7d589e9f-7522-408c-b7c8-42770920766f" type_id="msg_6e2baaf3b97dbeef01c0043275f9a0e7">
|
||||
<config_set_global name="global_messages"/>
|
||||
</component>
|
||||
<component name="gpio_adapter_common" uuid="e9da5e16-1f55-49be-87ec-af8cfd4a4105" type_id="gpio_adapter_common_57579b9ac814fe26bf95df0a384c36b6">
|
||||
<config_set_global name="global_gpio_adapter_common" quick_selection="default"/>
|
||||
</component>
|
||||
<component name="generic_uart" uuid="9dc7a034-9408-4852-9990-a713693635ee" type_id="generic_uart_8cae00565451cf2346eb1b8c624e73a6">
|
||||
<config_set_global name="global_uart"/>
|
||||
</component>
|
||||
<component name="generic_can" uuid="28ec81a8-d7ea-4363-9330-20b877c481f6" type_id="generic_can_1bfdd78b1af214566c1f23cf6a582d80">
|
||||
<config_set_global name="global_can"/>
|
||||
</component>
|
||||
<component name="uart_cmsis_common" uuid="774dd0a0-63ed-4846-b9d7-dfd082d810e3" type_id="uart_cmsis_common_9cb8e302497aa696fdbb5a4fd622c2a8">
|
||||
<config_set_global name="global_USART_CMSIS_common" quick_selection="default"/>
|
||||
</component>
|
||||
<component name="generic_enet" uuid="77cd333e-4adc-4c6e-8b18-bbe349d78182" type_id="generic_enet_74db5c914f0ddbe47d86af40cb77a619">
|
||||
<config_set_global name="global_enet"/>
|
||||
</component>
|
||||
</components>
|
||||
</periphs>
|
||||
<tee name="TEE" version="4.0" enabled="false" update_project_code="true">
|
||||
<generated_project_files/>
|
||||
<tee_profile>
|
||||
<processor_version>N/A</processor_version>
|
||||
</tee_profile>
|
||||
</tee>
|
||||
</tools>
|
||||
</configuration>
|
||||
Reference in New Issue
Block a user