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KoDer
2026-05-06 19:51:30 +07:00
commit 3958b0edcf
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components/espressif__tinyusb/hw/bsp/imxrt/boards/mimxrt1024_evk/board.cmake
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set(MCU_VARIANT MIMXRT1024)
set(JLINK_DEVICE MIMXRT1024xxx5A)
set(PYOCD_TARGET mimxrt1024)
set(NXPLINK_DEVICE MIMXRT1024xxxxx:MIMXRT1024-EVK)
function(update_board TARGET)
target_sources(${TARGET} PUBLIC
${CMAKE_CURRENT_FUNCTION_LIST_DIR}/evkmimxrt1024_flexspi_nor_config.c
)
target_compile_definitions(${TARGET} PUBLIC
CPU_MIMXRT1024DAG5A
CFG_EXAMPLE_VIDEO_READONLY
#-Wno-error=array-bounds
)
endfunction()
components/espressif__tinyusb/hw/bsp/imxrt/boards/mimxrt1024_evk/board.h
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/*
* The MIT License (MIT)
*
* Copyright (c) 2019, Ha Thach (tinyusb.org)
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*
* This file is part of the TinyUSB stack.
*/
/* metadata:
name: i.MX RT1024 Evaluation Kit
url: https://www.nxp.com/design/design-center/development-boards-and-designs/i-mx-evaluation-and-development-boards/i-mx-rt1024-evaluation-kit:MIMXRT1024-EVK
*/
#ifndef BOARD_MIMXRT1024_EVK_H_
#define BOARD_MIMXRT1024_EVK_H_
// required since iMXRT MCUX-SDK include this file for board size
// RT1020-EVK #define BOARD_FLASH_SIZE (0x800000U)
#define BOARD_FLASH_SIZE (0x400000U) // builtin flash of RT1024
// LED: IOMUXC_GPIO_AD_B1_08_GPIO1_IO24
#define LED_PORT BOARD_INITPINS_USER_LED_GPIO
#define LED_PIN BOARD_INITPINS_USER_LED_PIN
#define LED_STATE_ON 1
// SW8 button: IOMUXC_SNVS_WAKEUP_GPIO5_IO00
#define BUTTON_PORT BOARD_INITPINS_USER_BUTTON_GPIO
#define BUTTON_PIN BOARD_INITPINS_USER_BUTTON_PIN
#define BUTTON_STATE_ACTIVE 0
// UART: IOMUXC_GPIO_AD_B0_07_LPUART1_RX, IOMUXC_GPIO_AD_B0_06_LPUART1_TX
#define UART_PORT LPUART1
#define UART_CLK_ROOT BOARD_BOOTCLOCKRUN_UART_CLK_ROOT
static inline void BOARD_ConfigMPU(void) {
}
#endif
components/espressif__tinyusb/hw/bsp/imxrt/boards/mimxrt1024_evk/board.mk
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CFLAGS += -DCPU_MIMXRT1024DAG5A
MCU_VARIANT = MIMXRT1024
# warnings caused by mcu driver
CFLAGS += -Wno-error=array-bounds
# For flash-jlink target
JLINK_DEVICE = MIMXRT1024xxx5A
# For flash-pyocd target
PYOCD_TARGET = mimxrt1024
# flash using pyocd
flash: flash-pyocd
components/espressif__tinyusb/hw/bsp/imxrt/boards/mimxrt1024_evk/board/clock_config.c
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/*
* How to setup clock using clock driver functions:
*
* 1. Call CLOCK_InitXXXPLL() to configure corresponding PLL clock.
*
* 2. Call CLOCK_InitXXXpfd() to configure corresponding PLL pfd clock.
*
* 3. Call CLOCK_SetMux() to configure corresponding clock source for target clock out.
*
* 4. Call CLOCK_SetDiv() to configure corresponding clock divider for target clock out.
*
* 5. Call CLOCK_SetXtalFreq() to set XTAL frequency based on board settings.
*
*/
/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
!!GlobalInfo
product: Clocks v11.0
processor: MIMXRT1024xxxxx
package_id: MIMXRT1024DAG5A
mcu_data: ksdk2_0
processor_version: 13.0.2
board: MIMXRT1024-EVK
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
#include "clock_config.h"
#include "fsl_iomuxc.h"
/*******************************************************************************
* Definitions
******************************************************************************/
/*******************************************************************************
* Variables
******************************************************************************/
/*******************************************************************************
************************ BOARD_InitBootClocks function ************************
******************************************************************************/
void BOARD_InitBootClocks(void)
{
BOARD_BootClockRUN();
}
/*******************************************************************************
********************** Configuration BOARD_BootClockRUN ***********************
******************************************************************************/
/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
!!Configuration
name: BOARD_BootClockRUN
called_from_default_init: true
outputs:
- {id: AHB_CLK_ROOT.outFreq, value: 500 MHz}
- {id: CAN_CLK_ROOT.outFreq, value: 40 MHz}
- {id: CKIL_SYNC_CLK_ROOT.outFreq, value: 32.768 kHz}
- {id: CLK_1M.outFreq, value: 1 MHz}
- {id: CLK_24M.outFreq, value: 24 MHz}
- {id: ENET_500M_REF_CLK.outFreq, value: 500 MHz}
- {id: FLEXIO1_CLK_ROOT.outFreq, value: 30 MHz}
- {id: FLEXSPI_CLK_ROOT.outFreq, value: 132 MHz}
- {id: GPT1_ipg_clk_highfreq.outFreq, value: 62.5 MHz}
- {id: GPT2_ipg_clk_highfreq.outFreq, value: 62.5 MHz}
- {id: IPG_CLK_ROOT.outFreq, value: 125 MHz}
- {id: LPI2C_CLK_ROOT.outFreq, value: 60 MHz}
- {id: LPSPI_CLK_ROOT.outFreq, value: 105.6 MHz}
- {id: MQS_MCLK.outFreq, value: 1080/17 MHz}
- {id: PERCLK_CLK_ROOT.outFreq, value: 62.5 MHz}
- {id: SAI1_CLK_ROOT.outFreq, value: 1080/17 MHz}
- {id: SAI1_MCLK1.outFreq, value: 1080/17 MHz}
- {id: SAI1_MCLK2.outFreq, value: 1080/17 MHz}
- {id: SAI1_MCLK3.outFreq, value: 30 MHz}
- {id: SAI2_CLK_ROOT.outFreq, value: 1080/17 MHz}
- {id: SAI2_MCLK1.outFreq, value: 1080/17 MHz}
- {id: SAI2_MCLK3.outFreq, value: 30 MHz}
- {id: SAI3_CLK_ROOT.outFreq, value: 1080/17 MHz}
- {id: SAI3_MCLK1.outFreq, value: 1080/17 MHz}
- {id: SAI3_MCLK3.outFreq, value: 30 MHz}
- {id: SEMC_CLK_ROOT.outFreq, value: 62.5 MHz}
- {id: SPDIF0_CLK_ROOT.outFreq, value: 30 MHz}
- {id: TRACE_CLK_ROOT.outFreq, value: 132 MHz}
- {id: UART_CLK_ROOT.outFreq, value: 80 MHz}
- {id: USBPHY1_CLK.outFreq, value: 480 MHz}
- {id: USDHC1_CLK_ROOT.outFreq, value: 176 MHz}
- {id: USDHC2_CLK_ROOT.outFreq, value: 176 MHz}
settings:
- {id: CCM.AHB_PODF.scale, value: '1', locked: true}
- {id: CCM.ARM_PODF.scale, value: '1', locked: true}
- {id: CCM.FLEXSPI_PODF.scale, value: '4', locked: true}
- {id: CCM.FLEXSPI_SEL.sel, value: CCM_ANALOG.PLL2_PFD2_CLK}
- {id: CCM.IPG_PODF.scale, value: '4'}
- {id: CCM.LPSPI_PODF.scale, value: '5', locked: true}
- {id: CCM.PERCLK_PODF.scale, value: '2', locked: true}
- {id: CCM.PRE_PERIPH_CLK_SEL.sel, value: CCM.ARM_PODF}
- {id: CCM.SEMC_PODF.scale, value: '8'}
- {id: CCM.TRACE_CLK_SEL.sel, value: CCM_ANALOG.PLL2_MAIN_CLK}
- {id: CCM.TRACE_PODF.scale, value: '4', locked: true}
- {id: CCM.USDHC1_PODF.scale, value: '3', locked: true}
- {id: CCM.USDHC2_PODF.scale, value: '3', locked: true}
- {id: CCM_ANALOG.PLL2.denom, value: '1', locked: true}
- {id: CCM_ANALOG.PLL2.num, value: '0', locked: true}
- {id: CCM_ANALOG.PLL2_BYPASS.sel, value: CCM_ANALOG.PLL2_OUT_CLK}
- {id: CCM_ANALOG.PLL2_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD0}
- {id: CCM_ANALOG.PLL2_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD1}
- {id: CCM_ANALOG.PLL2_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD2}
- {id: CCM_ANALOG.PLL2_PFD2_DIV.scale, value: '18', locked: true}
- {id: CCM_ANALOG.PLL2_PFD2_MUL.scale, value: '18', locked: true}
- {id: CCM_ANALOG.PLL2_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD3}
- {id: CCM_ANALOG.PLL2_PFD3_DIV.scale, value: '18', locked: true}
- {id: CCM_ANALOG.PLL2_PFD3_MUL.scale, value: '18', locked: true}
- {id: CCM_ANALOG.PLL3_BYPASS.sel, value: CCM_ANALOG.PLL3}
- {id: CCM_ANALOG.PLL3_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD0}
- {id: CCM_ANALOG.PLL3_PFD0_DIV.scale, value: '22', locked: true}
- {id: CCM_ANALOG.PLL3_PFD0_MUL.scale, value: '18', locked: true}
- {id: CCM_ANALOG.PLL3_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD1}
- {id: CCM_ANALOG.PLL3_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD2}
- {id: CCM_ANALOG.PLL3_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD3}
- {id: CCM_ANALOG.PLL3_PFD3_DIV.scale, value: '18', locked: true}
- {id: CCM_ANALOG.PLL3_PFD3_MUL.scale, value: '18', locked: true}
- {id: CCM_ANALOG.PLL4.denom, value: '50'}
- {id: CCM_ANALOG.PLL4.div, value: '47'}
- {id: CCM_ANALOG.PLL6_BYPASS.sel, value: CCM_ANALOG.PLL6}
- {id: CCM_ANALOG_PLL_ENET_ENABLE_CFG, value: Disabled}
- {id: CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_CFG, value: Disabled}
- {id: CCM_ANALOG_PLL_USB1_EN_USB_CLKS_CFG, value: Enabled}
- {id: CCM_ANALOG_PLL_USB1_EN_USB_CLKS_OUT_CFG, value: Enabled}
- {id: CCM_ANALOG_PLL_USB1_POWER_CFG, value: 'Yes'}
sources:
- {id: XTALOSC24M.RTC_OSC.outFreq, value: 32.768 kHz, enabled: true}
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
/*******************************************************************************
* Variables for BOARD_BootClockRUN configuration
******************************************************************************/
const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN =
{
.loopDivider = 1, /* PLL loop divider, Fout = Fin * ( 20 + loopDivider*2 + numerator / denominator ) */
.numerator = 0, /* 30 bit numerator of fractional loop divider */
.denominator = 1, /* 30 bit denominator of fractional loop divider */
.src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
};
const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN =
{
.loopDivider = 0, /* PLL loop divider, Fout = Fin * 20 */
.src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
};
const clock_enet_pll_config_t enetPllConfig_BOARD_BootClockRUN =
{
.enableClkOutput = false, /* Disable the PLL providing the ENET 125MHz reference clock */
.enableClkOutput500M = true, /* Enable the PLL providing the ENET 500MHz reference clock */
.enableClkOutput25M = false, /* Disable the PLL providing the ENET 25MHz reference clock */
.loopDivider = 1, /* Set frequency of ethernet reference clock to 50 MHz */
.src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
};
/*******************************************************************************
* Code for BOARD_BootClockRUN configuration
******************************************************************************/
void BOARD_BootClockRUN(void)
{
/* Init RTC OSC clock frequency. */
CLOCK_SetRtcXtalFreq(32768U);
/* Enable 1MHz clock output. */
XTALOSC24M->OSC_CONFIG2 |= XTALOSC24M_OSC_CONFIG2_ENABLE_1M_MASK;
/* Use free 1MHz clock output. */
XTALOSC24M->OSC_CONFIG2 &= ~XTALOSC24M_OSC_CONFIG2_MUX_1M_MASK;
/* Set XTAL 24MHz clock frequency. */
CLOCK_SetXtalFreq(24000000U);
/* Enable XTAL 24MHz clock source. */
CLOCK_InitExternalClk(0);
/* Enable internal RC. */
CLOCK_InitRcOsc24M();
/* Switch clock source to external OSC. */
CLOCK_SwitchOsc(kCLOCK_XtalOsc);
/* Set Oscillator ready counter value. */
CCM->CCR = (CCM->CCR & (~CCM_CCR_OSCNT_MASK)) | CCM_CCR_OSCNT(127);
/* Setting PeriphClk2Mux and PeriphMux to provide stable clock before PLLs are initialed */
CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 1); /* Set PERIPH_CLK2 MUX to OSC */
CLOCK_SetMux(kCLOCK_PeriphMux, 1); /* Set PERIPH_CLK MUX to PERIPH_CLK2 */
/* Setting the VDD_SOC to 1.25V. It is necessary to config AHB to 500Mhz. */
DCDC->REG3 = (DCDC->REG3 & (~DCDC_REG3_TRG_MASK)) | DCDC_REG3_TRG(0x12);
/* Waiting for DCDC_STS_DC_OK bit is asserted */
while (DCDC_REG0_STS_DC_OK_MASK != (DCDC_REG0_STS_DC_OK_MASK & DCDC->REG0))
{
}
/* Set AHB_PODF. */
CLOCK_SetDiv(kCLOCK_AhbDiv, 0);
/* Disable IPG clock gate. */
CLOCK_DisableClock(kCLOCK_Adc1);
CLOCK_DisableClock(kCLOCK_Adc2);
CLOCK_DisableClock(kCLOCK_Xbar1);
CLOCK_DisableClock(kCLOCK_Xbar2);
/* Set IPG_PODF. */
CLOCK_SetDiv(kCLOCK_IpgDiv, 3);
/* Set ARM_PODF. */
CLOCK_SetDiv(kCLOCK_ArmDiv, 0);
/* Set PERIPH_CLK2_PODF. */
CLOCK_SetDiv(kCLOCK_PeriphClk2Div, 0);
/* Disable PERCLK clock gate. */
CLOCK_DisableClock(kCLOCK_Gpt1);
CLOCK_DisableClock(kCLOCK_Gpt1S);
CLOCK_DisableClock(kCLOCK_Gpt2);
CLOCK_DisableClock(kCLOCK_Gpt2S);
CLOCK_DisableClock(kCLOCK_Pit);
/* Set PERCLK_PODF. */
CLOCK_SetDiv(kCLOCK_PerclkDiv, 1);
/* Disable USDHC1 clock gate. */
CLOCK_DisableClock(kCLOCK_Usdhc1);
/* Set USDHC1_PODF. */
CLOCK_SetDiv(kCLOCK_Usdhc1Div, 2);
/* Set Usdhc1 clock source. */
CLOCK_SetMux(kCLOCK_Usdhc1Mux, 0);
/* Disable USDHC2 clock gate. */
CLOCK_DisableClock(kCLOCK_Usdhc2);
/* Set USDHC2_PODF. */
CLOCK_SetDiv(kCLOCK_Usdhc2Div, 2);
/* Set Usdhc2 clock source. */
CLOCK_SetMux(kCLOCK_Usdhc2Mux, 0);
/* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd.
* With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left unchanged.
* Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as well.*/
#ifndef SKIP_SYSCLK_INIT
/* Disable Semc clock gate. */
CLOCK_DisableClock(kCLOCK_Semc);
/* Set SEMC_PODF. */
CLOCK_SetDiv(kCLOCK_SemcDiv, 7);
/* Set Semc alt clock source. */
CLOCK_SetMux(kCLOCK_SemcAltMux, 0);
/* Set Semc clock source. */
CLOCK_SetMux(kCLOCK_SemcMux, 0);
#endif
/* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd.
* With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged.
* Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/
#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1))
/* Disable Flexspi clock gate. */
CLOCK_DisableClock(kCLOCK_FlexSpi);
/* Set FLEXSPI_PODF. */
CLOCK_SetDiv(kCLOCK_FlexspiDiv, 3);
/* Set Flexspi clock source. */
CLOCK_SetMux(kCLOCK_FlexspiMux, 2);
#endif
/* Disable LPSPI clock gate. */
CLOCK_DisableClock(kCLOCK_Lpspi1);
CLOCK_DisableClock(kCLOCK_Lpspi2);
CLOCK_DisableClock(kCLOCK_Lpspi3);
CLOCK_DisableClock(kCLOCK_Lpspi4);
/* Set LPSPI_PODF. */
CLOCK_SetDiv(kCLOCK_LpspiDiv, 4);
/* Set Lpspi clock source. */
CLOCK_SetMux(kCLOCK_LpspiMux, 2);
/* Disable TRACE clock gate. */
CLOCK_DisableClock(kCLOCK_Trace);
/* Set TRACE_PODF. */
CLOCK_SetDiv(kCLOCK_TraceDiv, 3);
/* Set Trace clock source. */
CLOCK_SetMux(kCLOCK_TraceMux, 0);
/* Disable SAI1 clock gate. */
CLOCK_DisableClock(kCLOCK_Sai1);
/* Set SAI1_CLK_PRED. */
CLOCK_SetDiv(kCLOCK_Sai1PreDiv, 3);
/* Set SAI1_CLK_PODF. */
CLOCK_SetDiv(kCLOCK_Sai1Div, 1);
/* Set Sai1 clock source. */
CLOCK_SetMux(kCLOCK_Sai1Mux, 0);
/* Disable SAI2 clock gate. */
CLOCK_DisableClock(kCLOCK_Sai2);
/* Set SAI2_CLK_PRED. */
CLOCK_SetDiv(kCLOCK_Sai2PreDiv, 3);
/* Set SAI2_CLK_PODF. */
CLOCK_SetDiv(kCLOCK_Sai2Div, 1);
/* Set Sai2 clock source. */
CLOCK_SetMux(kCLOCK_Sai2Mux, 0);
/* Disable SAI3 clock gate. */
CLOCK_DisableClock(kCLOCK_Sai3);
/* Set SAI3_CLK_PRED. */
CLOCK_SetDiv(kCLOCK_Sai3PreDiv, 3);
/* Set SAI3_CLK_PODF. */
CLOCK_SetDiv(kCLOCK_Sai3Div, 1);
/* Set Sai3 clock source. */
CLOCK_SetMux(kCLOCK_Sai3Mux, 0);
/* Disable Lpi2c clock gate. */
CLOCK_DisableClock(kCLOCK_Lpi2c1);
CLOCK_DisableClock(kCLOCK_Lpi2c2);
CLOCK_DisableClock(kCLOCK_Lpi2c3);
/* Set LPI2C_CLK_PODF. */
CLOCK_SetDiv(kCLOCK_Lpi2cDiv, 0);
/* Set Lpi2c clock source. */
CLOCK_SetMux(kCLOCK_Lpi2cMux, 0);
/* Disable CAN clock gate. */
CLOCK_DisableClock(kCLOCK_Can1);
CLOCK_DisableClock(kCLOCK_Can2);
CLOCK_DisableClock(kCLOCK_Can1S);
CLOCK_DisableClock(kCLOCK_Can2S);
/* Set CAN_CLK_PODF. */
CLOCK_SetDiv(kCLOCK_CanDiv, 1);
/* Set Can clock source. */
CLOCK_SetMux(kCLOCK_CanMux, 2);
/* Disable UART clock gate. */
CLOCK_DisableClock(kCLOCK_Lpuart1);
CLOCK_DisableClock(kCLOCK_Lpuart2);
CLOCK_DisableClock(kCLOCK_Lpuart3);
CLOCK_DisableClock(kCLOCK_Lpuart4);
CLOCK_DisableClock(kCLOCK_Lpuart5);
CLOCK_DisableClock(kCLOCK_Lpuart6);
CLOCK_DisableClock(kCLOCK_Lpuart7);
CLOCK_DisableClock(kCLOCK_Lpuart8);
/* Set UART_CLK_PODF. */
CLOCK_SetDiv(kCLOCK_UartDiv, 0);
/* Set Uart clock source. */
CLOCK_SetMux(kCLOCK_UartMux, 0);
/* Disable SPDIF clock gate. */
CLOCK_DisableClock(kCLOCK_Spdif);
/* Set SPDIF0_CLK_PRED. */
CLOCK_SetDiv(kCLOCK_Spdif0PreDiv, 1);
/* Set SPDIF0_CLK_PODF. */
CLOCK_SetDiv(kCLOCK_Spdif0Div, 7);
/* Set Spdif clock source. */
CLOCK_SetMux(kCLOCK_SpdifMux, 3);
/* Disable Flexio1 clock gate. */
CLOCK_DisableClock(kCLOCK_Flexio1);
/* Set FLEXIO1_CLK_PRED. */
CLOCK_SetDiv(kCLOCK_Flexio1PreDiv, 1);
/* Set FLEXIO1_CLK_PODF. */
CLOCK_SetDiv(kCLOCK_Flexio1Div, 7);
/* Set Flexio1 clock source. */
CLOCK_SetMux(kCLOCK_Flexio1Mux, 3);
/* Set Pll3 sw clock source. */
CLOCK_SetMux(kCLOCK_Pll3SwMux, 0);
/* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd.
* With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left unchanged.
* Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as well.*/
#ifndef SKIP_SYSCLK_INIT
#if defined(XIP_BOOT_HEADER_DCD_ENABLE) && (XIP_BOOT_HEADER_DCD_ENABLE == 1)
#warning "SKIP_SYSCLK_INIT should be defined to keep system pll (selected to be SEMC source clock in SDK projects) unchanged."
#endif
/* Init System PLL. */
CLOCK_InitSysPll(&sysPllConfig_BOARD_BootClockRUN);
/* Init System pfd0. */
CLOCK_InitSysPfd(kCLOCK_Pfd0, 27);
/* Init System pfd1. */
CLOCK_InitSysPfd(kCLOCK_Pfd1, 16);
/* Init System pfd2. */
CLOCK_InitSysPfd(kCLOCK_Pfd2, 18);
/* Init System pfd3. */
CLOCK_InitSysPfd(kCLOCK_Pfd3, 18);
#endif
/* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd.
* With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged.
* Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/
#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1))
/* Init Usb1 PLL. */
CLOCK_InitUsb1Pll(&usb1PllConfig_BOARD_BootClockRUN);
/* Init Usb1 pfd0. */
CLOCK_InitUsb1Pfd(kCLOCK_Pfd0, 22);
/* Init Usb1 pfd1. */
CLOCK_InitUsb1Pfd(kCLOCK_Pfd1, 16);
/* Init Usb1 pfd2. */
CLOCK_InitUsb1Pfd(kCLOCK_Pfd2, 17);
/* Init Usb1 pfd3. */
CLOCK_InitUsb1Pfd(kCLOCK_Pfd3, 18);
#endif
/* DeInit Audio PLL. */
CLOCK_DeinitAudioPll();
/* Bypass Audio PLL. */
CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllAudio, 1);
/* Set divider for Audio PLL. */
CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK;
CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK;
/* Enable Audio PLL output. */
CCM_ANALOG->PLL_AUDIO |= CCM_ANALOG_PLL_AUDIO_ENABLE_MASK;
/* Init Enet PLL. */
CLOCK_InitEnetPll(&enetPllConfig_BOARD_BootClockRUN);
/* Set preperiph clock source. */
CLOCK_SetMux(kCLOCK_PrePeriphMux, 3);
/* Set periph clock source. */
CLOCK_SetMux(kCLOCK_PeriphMux, 0);
/* Set periph clock2 clock source. */
CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 0);
/* Set per clock source. */
CLOCK_SetMux(kCLOCK_PerclkMux, 0);
/* Set clock out1 divider. */
CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_DIV_MASK)) | CCM_CCOSR_CLKO1_DIV(0);
/* Set clock out1 source. */
CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_SEL_MASK)) | CCM_CCOSR_CLKO1_SEL(1);
/* Set clock out2 divider. */
CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_DIV_MASK)) | CCM_CCOSR_CLKO2_DIV(0);
/* Set clock out2 source. */
CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_SEL_MASK)) | CCM_CCOSR_CLKO2_SEL(3);
/* Set clock out1 drives clock out1. */
CCM->CCOSR &= ~CCM_CCOSR_CLK_OUT_SEL_MASK;
/* Disable clock out1. */
CCM->CCOSR &= ~CCM_CCOSR_CLKO1_EN_MASK;
/* Disable clock out2. */
CCM->CCOSR &= ~CCM_CCOSR_CLKO2_EN_MASK;
/* Set SAI1 MCLK1 clock source. */
IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk1Sel, 0);
/* Set SAI1 MCLK2 clock source. */
IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk2Sel, 0);
/* Set SAI1 MCLK3 clock source. */
IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk3Sel, 0);
/* Set SAI2 MCLK3 clock source. */
IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI2MClk3Sel, 0);
/* Set SAI3 MCLK3 clock source. */
IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI3MClk3Sel, 0);
/* Set MQS configuration. */
IOMUXC_MQSConfig(IOMUXC_GPR,kIOMUXC_MqsPwmOverSampleRate32, 0);
/* Set ENET Ref clock source. */
#if defined(IOMUXC_GPR_GPR1_ENET_REF_CLK_DIR_MASK)
IOMUXC_GPR->GPR1 &= ~IOMUXC_GPR_GPR1_ENET_REF_CLK_DIR_MASK;
#elif defined(IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK)
/* Backward compatibility for original bitfield name */
IOMUXC_GPR->GPR1 &= ~IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK;
#else
#error "Neither IOMUXC_GPR_GPR1_ENET_REF_CLK_DIR_MASK nor IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK is defined."
#endif /* defined(IOMUXC_GPR_GPR1_ENET_REF_CLK_DIR_MASK) */
/* Set GPT1 High frequency reference clock source. */
IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK;
/* Set GPT2 High frequency reference clock source. */
IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK;
/* Set SystemCoreClock variable. */
SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK;
}
components/espressif__tinyusb/hw/bsp/imxrt/boards/mimxrt1024_evk/board/clock_config.h
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#ifndef _CLOCK_CONFIG_H_
#define _CLOCK_CONFIG_H_
#include "fsl_common.h"
/*******************************************************************************
* Definitions
******************************************************************************/
#define BOARD_XTAL0_CLK_HZ 24000000U /*!< Board xtal0 frequency in Hz */
#define BOARD_XTAL32K_CLK_HZ 32768U /*!< Board xtal32k frequency in Hz */
/*******************************************************************************
************************ BOARD_InitBootClocks function ************************
******************************************************************************/
#if defined(__cplusplus)
extern "C" {
#endif /* __cplusplus*/
/*!
* @brief This function executes default configuration of clocks.
*
*/
void BOARD_InitBootClocks(void);
#if defined(__cplusplus)
}
#endif /* __cplusplus*/
/*******************************************************************************
********************** Configuration BOARD_BootClockRUN ***********************
******************************************************************************/
/*******************************************************************************
* Definitions for BOARD_BootClockRUN configuration
******************************************************************************/
#define BOARD_BOOTCLOCKRUN_CORE_CLOCK 500000000U /*!< Core clock frequency: 500000000Hz */
/* Clock outputs (values are in Hz): */
#define BOARD_BOOTCLOCKRUN_AHB_CLK_ROOT 500000000UL
#define BOARD_BOOTCLOCKRUN_CAN_CLK_ROOT 40000000UL
#define BOARD_BOOTCLOCKRUN_CKIL_SYNC_CLK_ROOT 32768UL
#define BOARD_BOOTCLOCKRUN_CLKO1_CLK 0UL
#define BOARD_BOOTCLOCKRUN_CLKO2_CLK 0UL
#define BOARD_BOOTCLOCKRUN_CLK_1M 1000000UL
#define BOARD_BOOTCLOCKRUN_CLK_24M 24000000UL
#define BOARD_BOOTCLOCKRUN_ENET_125M_CLK 0UL
#define BOARD_BOOTCLOCKRUN_ENET_25M_REF_CLK 0UL
#define BOARD_BOOTCLOCKRUN_ENET_500M_REF_CLK 500000000UL
#define BOARD_BOOTCLOCKRUN_ENET_REF_CLK 0UL
#define BOARD_BOOTCLOCKRUN_ENET_TX_CLK 0UL
#define BOARD_BOOTCLOCKRUN_FLEXIO1_CLK_ROOT 30000000UL
#define BOARD_BOOTCLOCKRUN_FLEXSPI_CLK_ROOT 132000000UL
#define BOARD_BOOTCLOCKRUN_GPT1_IPG_CLK_HIGHFREQ 62500000UL
#define BOARD_BOOTCLOCKRUN_GPT2_IPG_CLK_HIGHFREQ 62500000UL
#define BOARD_BOOTCLOCKRUN_IPG_CLK_ROOT 125000000UL
#define BOARD_BOOTCLOCKRUN_LPI2C_CLK_ROOT 60000000UL
#define BOARD_BOOTCLOCKRUN_LPSPI_CLK_ROOT 105600000UL
#define BOARD_BOOTCLOCKRUN_MQS_MCLK 63529411UL
#define BOARD_BOOTCLOCKRUN_PERCLK_CLK_ROOT 62500000UL
#define BOARD_BOOTCLOCKRUN_SAI1_CLK_ROOT 63529411UL
#define BOARD_BOOTCLOCKRUN_SAI1_MCLK1 63529411UL
#define BOARD_BOOTCLOCKRUN_SAI1_MCLK2 63529411UL
#define BOARD_BOOTCLOCKRUN_SAI1_MCLK3 30000000UL
#define BOARD_BOOTCLOCKRUN_SAI2_CLK_ROOT 63529411UL
#define BOARD_BOOTCLOCKRUN_SAI2_MCLK1 63529411UL
#define BOARD_BOOTCLOCKRUN_SAI2_MCLK2 0UL
#define BOARD_BOOTCLOCKRUN_SAI2_MCLK3 30000000UL
#define BOARD_BOOTCLOCKRUN_SAI3_CLK_ROOT 63529411UL
#define BOARD_BOOTCLOCKRUN_SAI3_MCLK1 63529411UL
#define BOARD_BOOTCLOCKRUN_SAI3_MCLK2 0UL
#define BOARD_BOOTCLOCKRUN_SAI3_MCLK3 30000000UL
#define BOARD_BOOTCLOCKRUN_SEMC_CLK_ROOT 62500000UL
#define BOARD_BOOTCLOCKRUN_SPDIF0_CLK_ROOT 30000000UL
#define BOARD_BOOTCLOCKRUN_SPDIF0_EXTCLK_OUT 0UL
#define BOARD_BOOTCLOCKRUN_TRACE_CLK_ROOT 132000000UL
#define BOARD_BOOTCLOCKRUN_UART_CLK_ROOT 80000000UL
#define BOARD_BOOTCLOCKRUN_USBPHY1_CLK 480000000UL
#define BOARD_BOOTCLOCKRUN_USDHC1_CLK_ROOT 176000000UL
#define BOARD_BOOTCLOCKRUN_USDHC2_CLK_ROOT 176000000UL
/*! @brief Usb1 PLL set for BOARD_BootClockRUN configuration.
*/
extern const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN;
/*! @brief Sys PLL for BOARD_BootClockRUN configuration.
*/
extern const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN;
/*! @brief Enet PLL set for BOARD_BootClockRUN configuration.
*/
extern const clock_enet_pll_config_t enetPllConfig_BOARD_BootClockRUN;
/*******************************************************************************
* API for BOARD_BootClockRUN configuration
******************************************************************************/
#if defined(__cplusplus)
extern "C" {
#endif /* __cplusplus*/
/*!
* @brief This function executes configuration of clocks.
*
*/
void BOARD_BootClockRUN(void);
#if defined(__cplusplus)
}
#endif /* __cplusplus*/
#endif /* _CLOCK_CONFIG_H_ */
components/espressif__tinyusb/hw/bsp/imxrt/boards/mimxrt1024_evk/board/pin_mux.c
Executable
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/***********************************************************************************************************************
* This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
* will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
**********************************************************************************************************************/
/*
* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
!!GlobalInfo
product: Pins v13.1
processor: MIMXRT1024xxxxx
package_id: MIMXRT1024DAG5A
mcu_data: ksdk2_0
processor_version: 13.0.2
board: MIMXRT1024-EVK
pin_labels:
- {pin_num: '52', pin_signal: WAKEUP, label: USER_BUTTON, identifier: USER_BUTTON}
- {pin_num: '82', pin_signal: GPIO_AD_B1_08, label: 'UART_TX/USER_LED/J17[4]', identifier: USER_LED}
power_domains: {NVCC_GPIO: '3.3'}
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
*/
#include "fsl_common.h"
#include "fsl_iomuxc.h"
#include "fsl_gpio.h"
#include "pin_mux.h"
/* FUNCTION ************************************************************************************************************
*
* Function Name : BOARD_InitBootPins
* Description : Calls initialization functions.
*
* END ****************************************************************************************************************/
void BOARD_InitBootPins(void) {
BOARD_InitPins();
BOARD_InitDEBUG_UARTPins();
/* GPIO_AD_B1_00~GPIO_AD_B1_05 can only be configured as flexspi function. Note that it can't be modified here */
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_00_FLEXSPI_A_DATA03,1U);
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_01_FLEXSPI_A_SCLK,1U);
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_02_FLEXSPI_A_DATA00,1U);
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_03_FLEXSPI_A_DATA02,1U);
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_04_FLEXSPI_A_DATA01,1U);
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_05_FLEXSPI_A_SS0_B,1U);
}
/*
* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
BOARD_InitPins:
- options: {callFromInitBoot: 'true', coreID: core0, enableClock: 'true'}
- pin_list:
- {pin_num: '52', peripheral: GPIO5, signal: 'gpio_io, 00', pin_signal: WAKEUP, direction: INPUT}
- {pin_num: '82', peripheral: GPIO1, signal: 'gpio_io, 24', pin_signal: GPIO_AD_B1_08, direction: OUTPUT}
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
*/
/* FUNCTION ************************************************************************************************************
*
* Function Name : BOARD_InitPins
* Description : Configures pin routing and optionally pin electrical features.
*
* END ****************************************************************************************************************/
void BOARD_InitPins(void) {
CLOCK_EnableClock(kCLOCK_Iomuxc); /* iomuxc clock (iomuxc_clk_enable): 0x03U */
CLOCK_EnableClock(kCLOCK_IomuxcSnvs); /* iomuxc_snvs clock (iomuxc_snvs_clk_enable): 0x03U */
/* GPIO configuration of USER_LED on GPIO_AD_B1_08 (pin 82) */
gpio_pin_config_t USER_LED_config = {
.direction = kGPIO_DigitalOutput,
.outputLogic = 0U,
.interruptMode = kGPIO_NoIntmode
};
/* Initialize GPIO functionality on GPIO_AD_B1_08 (pin 82) */
GPIO_PinInit(GPIO1, 24U, &USER_LED_config);
/* GPIO configuration of USER_BUTTON on WAKEUP (pin 52) */
gpio_pin_config_t USER_BUTTON_config = {
.direction = kGPIO_DigitalInput,
.outputLogic = 0U,
.interruptMode = kGPIO_NoIntmode
};
/* Initialize GPIO functionality on WAKEUP (pin 52) */
GPIO_PinInit(GPIO5, 0U, &USER_BUTTON_config);
IOMUXC_SetPinMux(
IOMUXC_GPIO_AD_B1_08_GPIO1_IO24, /* GPIO_AD_B1_08 is configured as GPIO1_IO24 */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_SNVS_WAKEUP_GPIO5_IO00, /* WAKEUP is configured as GPIO5_IO00 */
0U); /* Software Input On Field: Input Path is determined by functionality */
}
/*
* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
BOARD_InitDEBUG_UARTPins:
- options: {callFromInitBoot: 'true', coreID: core0, enableClock: 'true'}
- pin_list:
- {pin_num: '101', peripheral: LPUART1, signal: RX, pin_signal: GPIO_AD_B0_07}
- {pin_num: '105', peripheral: LPUART1, signal: TX, pin_signal: GPIO_AD_B0_06}
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
*/
/* FUNCTION ************************************************************************************************************
*
* Function Name : BOARD_InitDEBUG_UARTPins
* Description : Configures pin routing and optionally pin electrical features.
*
* END ****************************************************************************************************************/
void BOARD_InitDEBUG_UARTPins(void) {
CLOCK_EnableClock(kCLOCK_Iomuxc); /* iomuxc clock (iomuxc_clk_enable): 0x03U */
IOMUXC_SetPinMux(
IOMUXC_GPIO_AD_B0_06_LPUART1_TX, /* GPIO_AD_B0_06 is configured as LPUART1_TX */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_AD_B0_07_LPUART1_RX, /* GPIO_AD_B0_07 is configured as LPUART1_RX */
0U); /* Software Input On Field: Input Path is determined by functionality */
}
/*
* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
BOARD_InitSDRAMPins:
- options: {coreID: core0, enableClock: 'true'}
- pin_list:
- {pin_num: '142', peripheral: SEMC, signal: 'ADDR, 00', pin_signal: GPIO_EMC_16}
- {pin_num: '141', peripheral: SEMC, signal: 'ADDR, 01', pin_signal: GPIO_EMC_17}
- {pin_num: '140', peripheral: SEMC, signal: 'ADDR, 02', pin_signal: GPIO_EMC_18}
- {pin_num: '139', peripheral: SEMC, signal: 'ADDR, 03', pin_signal: GPIO_EMC_19}
- {pin_num: '138', peripheral: SEMC, signal: 'ADDR, 04', pin_signal: GPIO_EMC_20}
- {pin_num: '136', peripheral: SEMC, signal: 'ADDR, 06', pin_signal: GPIO_EMC_22}
- {pin_num: '137', peripheral: SEMC, signal: 'ADDR, 05', pin_signal: GPIO_EMC_21}
- {pin_num: '133', peripheral: SEMC, signal: 'ADDR, 07', pin_signal: GPIO_EMC_23}
- {pin_num: '132', peripheral: SEMC, signal: 'ADDR, 08', pin_signal: GPIO_EMC_24}
- {pin_num: '131', peripheral: SEMC, signal: 'ADDR, 09', pin_signal: GPIO_EMC_25}
- {pin_num: '143', peripheral: SEMC, signal: 'ADDR, 10', pin_signal: GPIO_EMC_15}
- {pin_num: '130', peripheral: SEMC, signal: 'ADDR, 11', pin_signal: GPIO_EMC_26}
- {pin_num: '129', peripheral: SEMC, signal: 'ADDR, 12', pin_signal: GPIO_EMC_27}
- {pin_num: '2', peripheral: SEMC, signal: 'BA, 0', pin_signal: GPIO_EMC_13}
- {pin_num: '1', peripheral: SEMC, signal: 'BA, 1', pin_signal: GPIO_EMC_14}
- {pin_num: '7', peripheral: SEMC, signal: semc_cas, pin_signal: GPIO_EMC_10}
- {pin_num: '127', peripheral: SEMC, signal: semc_cke, pin_signal: GPIO_EMC_29}
- {pin_num: '126', peripheral: SEMC, signal: semc_clk, pin_signal: GPIO_EMC_30}
- {pin_num: '3', peripheral: SEMC, signal: 'CS, 0', pin_signal: GPIO_EMC_12}
- {pin_num: '8', peripheral: SEMC, signal: semc_we, pin_signal: GPIO_EMC_09}
- {pin_num: '4', peripheral: SEMC, signal: semc_ras, pin_signal: GPIO_EMC_11}
- {pin_num: '128', peripheral: SEMC, signal: semc_dqs, pin_signal: GPIO_EMC_28}
- {pin_num: '125', peripheral: SEMC, signal: 'DM, 1', pin_signal: GPIO_EMC_31}
- {pin_num: '9', peripheral: SEMC, signal: 'DM, 0', pin_signal: GPIO_EMC_08}
- {pin_num: '117', peripheral: SEMC, signal: 'DATA, 15', pin_signal: GPIO_EMC_39}
- {pin_num: '118', peripheral: SEMC, signal: 'DATA, 14', pin_signal: GPIO_EMC_38}
- {pin_num: '119', peripheral: SEMC, signal: 'DATA, 13', pin_signal: GPIO_EMC_37}
- {pin_num: '120', peripheral: SEMC, signal: 'DATA, 12', pin_signal: GPIO_EMC_36}
- {pin_num: '122', peripheral: SEMC, signal: 'DATA, 10', pin_signal: GPIO_EMC_34}
- {pin_num: '121', peripheral: SEMC, signal: 'DATA, 11', pin_signal: GPIO_EMC_35}
- {pin_num: '123', peripheral: SEMC, signal: 'DATA, 09', pin_signal: GPIO_EMC_33}
- {pin_num: '124', peripheral: SEMC, signal: 'DATA, 08', pin_signal: GPIO_EMC_32}
- {pin_num: '10', peripheral: SEMC, signal: 'DATA, 07', pin_signal: GPIO_EMC_07}
- {pin_num: '12', peripheral: SEMC, signal: 'DATA, 06', pin_signal: GPIO_EMC_06}
- {pin_num: '13', peripheral: SEMC, signal: 'DATA, 05', pin_signal: GPIO_EMC_05}
- {pin_num: '14', peripheral: SEMC, signal: 'DATA, 04', pin_signal: GPIO_EMC_04}
- {pin_num: '15', peripheral: SEMC, signal: 'DATA, 03', pin_signal: GPIO_EMC_03}
- {pin_num: '16', peripheral: SEMC, signal: 'DATA, 02', pin_signal: GPIO_EMC_02}
- {pin_num: '17', peripheral: SEMC, signal: 'DATA, 01', pin_signal: GPIO_EMC_01}
- {pin_num: '18', peripheral: SEMC, signal: 'DATA, 00', pin_signal: GPIO_EMC_00}
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
*/
/* FUNCTION ************************************************************************************************************
*
* Function Name : BOARD_InitSDRAMPins
* Description : Configures pin routing and optionally pin electrical features.
*
* END ****************************************************************************************************************/
void BOARD_InitSDRAMPins(void) {
CLOCK_EnableClock(kCLOCK_Iomuxc); /* iomuxc clock (iomuxc_clk_enable): 0x03U */
IOMUXC_SetPinMux(
IOMUXC_GPIO_EMC_00_SEMC_DATA00, /* GPIO_EMC_00 is configured as SEMC_DATA00 */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_EMC_01_SEMC_DATA01, /* GPIO_EMC_01 is configured as SEMC_DATA01 */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_EMC_02_SEMC_DATA02, /* GPIO_EMC_02 is configured as SEMC_DATA02 */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_EMC_03_SEMC_DATA03, /* GPIO_EMC_03 is configured as SEMC_DATA03 */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_EMC_04_SEMC_DATA04, /* GPIO_EMC_04 is configured as SEMC_DATA04 */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_EMC_05_SEMC_DATA05, /* GPIO_EMC_05 is configured as SEMC_DATA05 */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_EMC_06_SEMC_DATA06, /* GPIO_EMC_06 is configured as SEMC_DATA06 */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_EMC_07_SEMC_DATA07, /* GPIO_EMC_07 is configured as SEMC_DATA07 */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_EMC_08_SEMC_DM00, /* GPIO_EMC_08 is configured as SEMC_DM00 */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_EMC_09_SEMC_WE, /* GPIO_EMC_09 is configured as SEMC_WE */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_EMC_10_SEMC_CAS, /* GPIO_EMC_10 is configured as SEMC_CAS */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_EMC_11_SEMC_RAS, /* GPIO_EMC_11 is configured as SEMC_RAS */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_EMC_12_SEMC_CS0, /* GPIO_EMC_12 is configured as SEMC_CS0 */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_EMC_13_SEMC_BA0, /* GPIO_EMC_13 is configured as SEMC_BA0 */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_EMC_14_SEMC_BA1, /* GPIO_EMC_14 is configured as SEMC_BA1 */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_EMC_15_SEMC_ADDR10, /* GPIO_EMC_15 is configured as SEMC_ADDR10 */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_EMC_16_SEMC_ADDR00, /* GPIO_EMC_16 is configured as SEMC_ADDR00 */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_EMC_17_SEMC_ADDR01, /* GPIO_EMC_17 is configured as SEMC_ADDR01 */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_EMC_18_SEMC_ADDR02, /* GPIO_EMC_18 is configured as SEMC_ADDR02 */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_EMC_19_SEMC_ADDR03, /* GPIO_EMC_19 is configured as SEMC_ADDR03 */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_EMC_20_SEMC_ADDR04, /* GPIO_EMC_20 is configured as SEMC_ADDR04 */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_EMC_21_SEMC_ADDR05, /* GPIO_EMC_21 is configured as SEMC_ADDR05 */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_EMC_22_SEMC_ADDR06, /* GPIO_EMC_22 is configured as SEMC_ADDR06 */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_EMC_23_SEMC_ADDR07, /* GPIO_EMC_23 is configured as SEMC_ADDR07 */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_EMC_24_SEMC_ADDR08, /* GPIO_EMC_24 is configured as SEMC_ADDR08 */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_EMC_25_SEMC_ADDR09, /* GPIO_EMC_25 is configured as SEMC_ADDR09 */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_EMC_26_SEMC_ADDR11, /* GPIO_EMC_26 is configured as SEMC_ADDR11 */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_EMC_27_SEMC_ADDR12, /* GPIO_EMC_27 is configured as SEMC_ADDR12 */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_EMC_28_SEMC_DQS, /* GPIO_EMC_28 is configured as SEMC_DQS */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_EMC_29_SEMC_CKE, /* GPIO_EMC_29 is configured as SEMC_CKE */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_EMC_30_SEMC_CLK, /* GPIO_EMC_30 is configured as SEMC_CLK */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_EMC_31_SEMC_DM01, /* GPIO_EMC_31 is configured as SEMC_DM01 */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_EMC_32_SEMC_DATA08, /* GPIO_EMC_32 is configured as SEMC_DATA08 */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_EMC_33_SEMC_DATA09, /* GPIO_EMC_33 is configured as SEMC_DATA09 */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_EMC_34_SEMC_DATA10, /* GPIO_EMC_34 is configured as SEMC_DATA10 */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_EMC_35_SEMC_DATA11, /* GPIO_EMC_35 is configured as SEMC_DATA11 */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_EMC_36_SEMC_DATA12, /* GPIO_EMC_36 is configured as SEMC_DATA12 */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_EMC_37_SEMC_DATA13, /* GPIO_EMC_37 is configured as SEMC_DATA13 */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_EMC_38_SEMC_DATA14, /* GPIO_EMC_38 is configured as SEMC_DATA14 */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_EMC_39_SEMC_DATA15, /* GPIO_EMC_39 is configured as SEMC_DATA15 */
0U); /* Software Input On Field: Input Path is determined by functionality */
}
/*
* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
BOARD_InitCANPins:
- options: {coreID: core0, enableClock: 'true'}
- pin_list:
- {pin_num: '32', peripheral: CAN1, signal: RX, pin_signal: GPIO_SD_B1_01}
- {pin_num: '33', peripheral: CAN1, signal: TX, pin_signal: GPIO_SD_B1_00}
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
*/
/* FUNCTION ************************************************************************************************************
*
* Function Name : BOARD_InitCANPins
* Description : Configures pin routing and optionally pin electrical features.
*
* END ****************************************************************************************************************/
void BOARD_InitCANPins(void) {
CLOCK_EnableClock(kCLOCK_Iomuxc); /* iomuxc clock (iomuxc_clk_enable): 0x03U */
IOMUXC_SetPinMux(
IOMUXC_GPIO_SD_B1_00_FLEXCAN1_TX, /* GPIO_SD_B1_00 is configured as FLEXCAN1_TX */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_SD_B1_01_FLEXCAN1_RX, /* GPIO_SD_B1_01 is configured as FLEXCAN1_RX */
0U); /* Software Input On Field: Input Path is determined by functionality */
}
/*
* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
BOARD_InitENETPins:
- options: {coreID: core0, enableClock: 'true'}
- pin_list:
- {pin_num: '97', peripheral: ENET, signal: enet_rx_en, pin_signal: GPIO_AD_B0_11}
- {pin_num: '84', peripheral: GPIO1, signal: 'gpio_io, 22', pin_signal: GPIO_AD_B1_06}
- {pin_num: '107', peripheral: GPIO1, signal: 'gpio_io, 04', pin_signal: GPIO_AD_B0_04}
- {pin_num: '100', peripheral: ENET, signal: enet_tx_clk, pin_signal: GPIO_AD_B0_08}
- {pin_num: '95', peripheral: ENET, signal: enet_tx_en, pin_signal: GPIO_AD_B0_13}
- {pin_num: '93', peripheral: ENET, signal: 'enet_tx_data, 1', pin_signal: GPIO_AD_B0_15}
- {pin_num: '94', peripheral: ENET, signal: 'enet_tx_data, 0', pin_signal: GPIO_AD_B0_14}
- {pin_num: '96', peripheral: ENET, signal: enet_rx_er, pin_signal: GPIO_AD_B0_12}
- {pin_num: '99', peripheral: ENET, signal: 'enet_rx_data, 1', pin_signal: GPIO_AD_B0_09}
- {pin_num: '98', peripheral: ENET, signal: 'enet_rx_data, 0', pin_signal: GPIO_AD_B0_10}
- {pin_num: '116', peripheral: ENET, signal: enet_mdio, pin_signal: GPIO_EMC_40}
- {pin_num: '115', peripheral: ENET, signal: enet_mdc, pin_signal: GPIO_EMC_41}
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
*/
/* FUNCTION ************************************************************************************************************
*
* Function Name : BOARD_InitENETPins
* Description : Configures pin routing and optionally pin electrical features.
*
* END ****************************************************************************************************************/
void BOARD_InitENETPins(void) {
CLOCK_EnableClock(kCLOCK_Iomuxc); /* iomuxc clock (iomuxc_clk_enable): 0x03U */
IOMUXC_SetPinMux(
IOMUXC_GPIO_AD_B0_04_GPIO1_IO04, /* GPIO_AD_B0_04 is configured as GPIO1_IO04 */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_AD_B0_08_ENET_TX_CLK, /* GPIO_AD_B0_08 is configured as ENET_TX_CLK */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_AD_B0_09_ENET_RDATA01, /* GPIO_AD_B0_09 is configured as ENET_RDATA01 */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_AD_B0_10_ENET_RDATA00, /* GPIO_AD_B0_10 is configured as ENET_RDATA00 */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_AD_B0_11_ENET_RX_EN, /* GPIO_AD_B0_11 is configured as ENET_RX_EN */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_AD_B0_12_ENET_RX_ER, /* GPIO_AD_B0_12 is configured as ENET_RX_ER */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_AD_B0_13_ENET_TX_EN, /* GPIO_AD_B0_13 is configured as ENET_TX_EN */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_AD_B0_14_ENET_TDATA00, /* GPIO_AD_B0_14 is configured as ENET_TDATA00 */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_AD_B0_15_ENET_TDATA01, /* GPIO_AD_B0_15 is configured as ENET_TDATA01 */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_AD_B1_06_GPIO1_IO22, /* GPIO_AD_B1_06 is configured as GPIO1_IO22 */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_EMC_40_ENET_MDIO, /* GPIO_EMC_40 is configured as ENET_MDIO */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_EMC_41_ENET_MDC, /* GPIO_EMC_41 is configured as ENET_MDC */
0U); /* Software Input On Field: Input Path is determined by functionality */
}
/*
* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
BOARD_InitUSDHCPins:
- options: {coreID: core0, enableClock: 'true'}
- pin_list:
- {pin_num: '45', peripheral: USDHC1, signal: usdhc_clk, pin_signal: GPIO_SD_B0_03}
- {pin_num: '46', peripheral: USDHC1, signal: usdhc_cmd, pin_signal: GPIO_SD_B0_02}
- {pin_num: '43', peripheral: USDHC1, signal: 'usdhc_data, 0', pin_signal: GPIO_SD_B0_04}
- {pin_num: '42', peripheral: USDHC1, signal: 'usdhc_data, 1', pin_signal: GPIO_SD_B0_05}
- {pin_num: '48', peripheral: USDHC1, signal: 'usdhc_data, 2', pin_signal: GPIO_SD_B0_00}
- {pin_num: '47', peripheral: USDHC1, signal: 'usdhc_data, 3', pin_signal: GPIO_SD_B0_01}
- {pin_num: '41', peripheral: GPIO3, signal: 'gpio_io, 19', pin_signal: GPIO_SD_B0_06}
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
*/
/* FUNCTION ************************************************************************************************************
*
* Function Name : BOARD_InitUSDHCPins
* Description : Configures pin routing and optionally pin electrical features.
*
* END ****************************************************************************************************************/
void BOARD_InitUSDHCPins(void) {
CLOCK_EnableClock(kCLOCK_Iomuxc); /* iomuxc clock (iomuxc_clk_enable): 0x03U */
IOMUXC_SetPinMux(
IOMUXC_GPIO_SD_B0_00_USDHC1_DATA2, /* GPIO_SD_B0_00 is configured as USDHC1_DATA2 */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_SD_B0_01_USDHC1_DATA3, /* GPIO_SD_B0_01 is configured as USDHC1_DATA3 */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_SD_B0_02_USDHC1_CMD, /* GPIO_SD_B0_02 is configured as USDHC1_CMD */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_SD_B0_03_USDHC1_CLK, /* GPIO_SD_B0_03 is configured as USDHC1_CLK */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_SD_B0_04_USDHC1_DATA0, /* GPIO_SD_B0_04 is configured as USDHC1_DATA0 */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_SD_B0_05_USDHC1_DATA1, /* GPIO_SD_B0_05 is configured as USDHC1_DATA1 */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_SD_B0_06_GPIO3_IO19, /* GPIO_SD_B0_06 is configured as GPIO3_IO19 */
0U); /* Software Input On Field: Input Path is determined by functionality */
}
/*
* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
BOARD_InitQSPIPins:
- options: {coreID: core0, enableClock: 'true'}
- pin_list:
- {pin_num: '24', peripheral: FLEXSPI, signal: FLEXSPI_A_SCLK, pin_signal: GPIO_SD_B1_07}
- {pin_num: '23', peripheral: FLEXSPI, signal: FLEXSPI_A_DATA0, pin_signal: GPIO_SD_B1_08}
- {pin_num: '21', peripheral: FLEXSPI, signal: FLEXSPI_A_DATA1, pin_signal: GPIO_SD_B1_10}
- {pin_num: '22', peripheral: FLEXSPI, signal: FLEXSPI_A_DATA2, pin_signal: GPIO_SD_B1_09}
- {pin_num: '25', peripheral: FLEXSPI, signal: FLEXSPI_A_DATA3, pin_signal: GPIO_SD_B1_06}
- {pin_num: '19', peripheral: FLEXSPI, signal: FLEXSPI_A_SS0_B, pin_signal: GPIO_SD_B1_11}
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
*/
/* FUNCTION ************************************************************************************************************
*
* Function Name : BOARD_InitQSPIPins
* Description : Configures pin routing and optionally pin electrical features.
*
* END ****************************************************************************************************************/
void BOARD_InitQSPIPins(void) {
CLOCK_EnableClock(kCLOCK_Iomuxc); /* iomuxc clock (iomuxc_clk_enable): 0x03U */
IOMUXC_SetPinMux(
IOMUXC_GPIO_SD_B1_06_FLEXSPI_A_DATA03, /* GPIO_SD_B1_06 is configured as FLEXSPI_A_DATA03 */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_SD_B1_07_FLEXSPI_A_SCLK, /* GPIO_SD_B1_07 is configured as FLEXSPI_A_SCLK */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_SD_B1_08_FLEXSPI_A_DATA00, /* GPIO_SD_B1_08 is configured as FLEXSPI_A_DATA00 */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_SD_B1_09_FLEXSPI_A_DATA02, /* GPIO_SD_B1_09 is configured as FLEXSPI_A_DATA02 */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_SD_B1_10_FLEXSPI_A_DATA01, /* GPIO_SD_B1_10 is configured as FLEXSPI_A_DATA01 */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_SD_B1_11_FLEXSPI_A_SS0_B, /* GPIO_SD_B1_11 is configured as FLEXSPI_A_SS0_B */
0U); /* Software Input On Field: Input Path is determined by functionality */
}
/***********************************************************************************************************************
* EOF
**********************************************************************************************************************/
components/espressif__tinyusb/hw/bsp/imxrt/boards/mimxrt1024_evk/board/pin_mux.h
Executable
+439
View File
@@ -0,0 +1,439 @@
/***********************************************************************************************************************
* This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
* will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
**********************************************************************************************************************/
#ifndef _PIN_MUX_H_
#define _PIN_MUX_H_
/***********************************************************************************************************************
* Definitions
**********************************************************************************************************************/
/* Define the flexspi macro. Note that it can't be modified here */
#define IOMUXC_GPIO_AD_B1_00_FLEXSPI_A_DATA03 0x401F80FCU, 0x1U, 0x401F8374U, 0x1U, 0x401F8270U
#define IOMUXC_GPIO_AD_B1_01_FLEXSPI_A_SCLK 0x401F8100U, 0x1U, 0x401F8378U, 0x1U, 0x401F8274U
#define IOMUXC_GPIO_AD_B1_02_FLEXSPI_A_DATA00 0x401F8104U, 0x1U, 0x401F8368U, 0x1U, 0x401F8278U
#define IOMUXC_GPIO_AD_B1_03_FLEXSPI_A_DATA02 0x401F8108U, 0x1U, 0x401F8370U, 0x1U, 0x401F827CU
#define IOMUXC_GPIO_AD_B1_04_FLEXSPI_A_DATA01 0x401F810CU, 0x1U, 0x401F836CU, 0x1U, 0x401F8280U
#define IOMUXC_GPIO_AD_B1_05_FLEXSPI_A_SS0_B 0x401F8110U, 0x1U, 0, 0, 0x401F8284U
/*! @brief Direction type */
typedef enum _pin_mux_direction
{
kPIN_MUX_DirectionInput = 0U, /* Input direction */
kPIN_MUX_DirectionOutput = 1U, /* Output direction */
kPIN_MUX_DirectionInputOrOutput = 2U /* Input or output direction */
} pin_mux_direction_t;
/*!
* @addtogroup pin_mux
* @{
*/
/***********************************************************************************************************************
* API
**********************************************************************************************************************/
#if defined(__cplusplus)
extern "C" {
#endif
/*!
* @brief Calls initialization functions.
*
*/
void BOARD_InitBootPins(void);
/* WAKEUP (number 52), USER_BUTTON */
#define BOARD_INITPINS_USER_BUTTON_GPIO GPIO5 /*!< GPIO device name: GPIO5 */
#define BOARD_INITPINS_USER_BUTTON_PORT GPIO5 /*!< PORT device name: GPIO5 */
#define BOARD_INITPINS_USER_BUTTON_PIN 0U /*!< GPIO5 pin index: 0 */
/* GPIO_AD_B1_08 (number 82), UART_TX/USER_LED/J17[4] */
#define BOARD_INITPINS_USER_LED_GPIO GPIO1 /*!< GPIO device name: GPIO1 */
#define BOARD_INITPINS_USER_LED_PORT GPIO1 /*!< PORT device name: GPIO1 */
#define BOARD_INITPINS_USER_LED_PIN 24U /*!< GPIO1 pin index: 24 */
/*!
* @brief Configures pin routing and optionally pin electrical features.
*
*/
void BOARD_InitPins(void);
/* GPIO_AD_B0_07 (number 101), UART1_RXD/J17[8] */
#define BOARD_INITDEBUG_UARTPINS_UART1_RXD_PERIPHERAL LPUART1 /*!< Device name: LPUART1 */
#define BOARD_INITDEBUG_UARTPINS_UART1_RXD_SIGNAL RX /*!< LPUART1 signal: RX */
/* GPIO_AD_B0_06 (number 105), UART1_TXD/J17[12] */
#define BOARD_INITDEBUG_UARTPINS_UART1_TXD_PERIPHERAL LPUART1 /*!< Device name: LPUART1 */
#define BOARD_INITDEBUG_UARTPINS_UART1_TXD_SIGNAL TX /*!< LPUART1 signal: TX */
/*!
* @brief Configures pin routing and optionally pin electrical features.
*
*/
void BOARD_InitDEBUG_UARTPins(void);
/* GPIO_EMC_16 (number 142), SEMC_A0/U14[23]/BOOT_MODE[0] */
#define BOARD_INITSDRAMPINS_SEMC_A0_PERIPHERAL SEMC /*!< Device name: SEMC */
#define BOARD_INITSDRAMPINS_SEMC_A0_SIGNAL ADDR /*!< SEMC signal: ADDR */
#define BOARD_INITSDRAMPINS_SEMC_A0_CHANNEL 0U /*!< SEMC ADDR channel: 00 */
/* GPIO_EMC_17 (number 141), SEMC_A1/U14[24]/BOOT_MODE[1] */
#define BOARD_INITSDRAMPINS_SEMC_A1_PERIPHERAL SEMC /*!< Device name: SEMC */
#define BOARD_INITSDRAMPINS_SEMC_A1_SIGNAL ADDR /*!< SEMC signal: ADDR */
#define BOARD_INITSDRAMPINS_SEMC_A1_CHANNEL 1U /*!< SEMC ADDR channel: 01 */
/* GPIO_EMC_18 (number 140), SEMC_A2/U14[25]/BT_CFG[0] */
#define BOARD_INITSDRAMPINS_SEMC_A2_PERIPHERAL SEMC /*!< Device name: SEMC */
#define BOARD_INITSDRAMPINS_SEMC_A2_SIGNAL ADDR /*!< SEMC signal: ADDR */
#define BOARD_INITSDRAMPINS_SEMC_A2_CHANNEL 2U /*!< SEMC ADDR channel: 02 */
/* GPIO_EMC_19 (number 139), SEMC_A3/U14[26]/BT_CFG[1] */
#define BOARD_INITSDRAMPINS_SEMC_A3_PERIPHERAL SEMC /*!< Device name: SEMC */
#define BOARD_INITSDRAMPINS_SEMC_A3_SIGNAL ADDR /*!< SEMC signal: ADDR */
#define BOARD_INITSDRAMPINS_SEMC_A3_CHANNEL 3U /*!< SEMC ADDR channel: 03 */
/* GPIO_EMC_20 (number 138), SEMC_A4/U14[29]/BT_CFG[2] */
#define BOARD_INITSDRAMPINS_SEMC_A4_PERIPHERAL SEMC /*!< Device name: SEMC */
#define BOARD_INITSDRAMPINS_SEMC_A4_SIGNAL ADDR /*!< SEMC signal: ADDR */
#define BOARD_INITSDRAMPINS_SEMC_A4_CHANNEL 4U /*!< SEMC ADDR channel: 04 */
/* GPIO_EMC_22 (number 136), SEMC_A6/U14[31]/BT_CFG[4] */
#define BOARD_INITSDRAMPINS_SEMC_A6_PERIPHERAL SEMC /*!< Device name: SEMC */
#define BOARD_INITSDRAMPINS_SEMC_A6_SIGNAL ADDR /*!< SEMC signal: ADDR */
#define BOARD_INITSDRAMPINS_SEMC_A6_CHANNEL 6U /*!< SEMC ADDR channel: 06 */
/* GPIO_EMC_21 (number 137), SEMC_A5/U14[30]/BT_CFG[3] */
#define BOARD_INITSDRAMPINS_SEMC_A5_PERIPHERAL SEMC /*!< Device name: SEMC */
#define BOARD_INITSDRAMPINS_SEMC_A5_SIGNAL ADDR /*!< SEMC signal: ADDR */
#define BOARD_INITSDRAMPINS_SEMC_A5_CHANNEL 5U /*!< SEMC ADDR channel: 05 */
/* GPIO_EMC_23 (number 133), SEMC_A7/U14[32]/BT_CFG[5] */
#define BOARD_INITSDRAMPINS_SEMC_A7_PERIPHERAL SEMC /*!< Device name: SEMC */
#define BOARD_INITSDRAMPINS_SEMC_A7_SIGNAL ADDR /*!< SEMC signal: ADDR */
#define BOARD_INITSDRAMPINS_SEMC_A7_CHANNEL 7U /*!< SEMC ADDR channel: 07 */
/* GPIO_EMC_24 (number 132), SEMC_A8/U14[33]/BT_CFG[6] */
#define BOARD_INITSDRAMPINS_SEMC_A8_PERIPHERAL SEMC /*!< Device name: SEMC */
#define BOARD_INITSDRAMPINS_SEMC_A8_SIGNAL ADDR /*!< SEMC signal: ADDR */
#define BOARD_INITSDRAMPINS_SEMC_A8_CHANNEL 8U /*!< SEMC ADDR channel: 08 */
/* GPIO_EMC_25 (number 131), SEMC_A9/U14[34]/BT_CFG[7] */
#define BOARD_INITSDRAMPINS_SEMC_A9_PERIPHERAL SEMC /*!< Device name: SEMC */
#define BOARD_INITSDRAMPINS_SEMC_A9_SIGNAL ADDR /*!< SEMC signal: ADDR */
#define BOARD_INITSDRAMPINS_SEMC_A9_CHANNEL 9U /*!< SEMC ADDR channel: 09 */
/* GPIO_EMC_15 (number 143), SEMC_A10/U14[22] */
#define BOARD_INITSDRAMPINS_SEMC_A10_PERIPHERAL SEMC /*!< Device name: SEMC */
#define BOARD_INITSDRAMPINS_SEMC_A10_SIGNAL ADDR /*!< SEMC signal: ADDR */
#define BOARD_INITSDRAMPINS_SEMC_A10_CHANNEL 10U /*!< SEMC ADDR channel: 10 */
/* GPIO_EMC_26 (number 130), SEMC_A11/U14[35]/BT_CFG[8] */
#define BOARD_INITSDRAMPINS_SEMC_A11_PERIPHERAL SEMC /*!< Device name: SEMC */
#define BOARD_INITSDRAMPINS_SEMC_A11_SIGNAL ADDR /*!< SEMC signal: ADDR */
#define BOARD_INITSDRAMPINS_SEMC_A11_CHANNEL 11U /*!< SEMC ADDR channel: 11 */
/* GPIO_EMC_27 (number 129), SEMC_A12/U14[36]/BT_CFG[9] */
#define BOARD_INITSDRAMPINS_SEMC_A12_PERIPHERAL SEMC /*!< Device name: SEMC */
#define BOARD_INITSDRAMPINS_SEMC_A12_SIGNAL ADDR /*!< SEMC signal: ADDR */
#define BOARD_INITSDRAMPINS_SEMC_A12_CHANNEL 12U /*!< SEMC ADDR channel: 12 */
/* GPIO_EMC_13 (number 2), SEMC_BA0/U14[20] */
#define BOARD_INITSDRAMPINS_SEMC_BA0_PERIPHERAL SEMC /*!< Device name: SEMC */
#define BOARD_INITSDRAMPINS_SEMC_BA0_SIGNAL BA /*!< SEMC signal: BA */
#define BOARD_INITSDRAMPINS_SEMC_BA0_CHANNEL 0U /*!< SEMC BA channel: 0 */
/* GPIO_EMC_14 (number 1), SEMC_BA1/U14[21] */
#define BOARD_INITSDRAMPINS_SEMC_BA1_PERIPHERAL SEMC /*!< Device name: SEMC */
#define BOARD_INITSDRAMPINS_SEMC_BA1_SIGNAL BA /*!< SEMC signal: BA */
#define BOARD_INITSDRAMPINS_SEMC_BA1_CHANNEL 1U /*!< SEMC BA channel: 1 */
/* GPIO_EMC_10 (number 7), SEMC_CAS/U14[17] */
#define BOARD_INITSDRAMPINS_SEMC_CAS_PERIPHERAL SEMC /*!< Device name: SEMC */
#define BOARD_INITSDRAMPINS_SEMC_CAS_SIGNAL semc_cas /*!< SEMC signal: semc_cas */
/* GPIO_EMC_29 (number 127), SEMC_CKE/U14[37] */
#define BOARD_INITSDRAMPINS_SEMC_CKE_PERIPHERAL SEMC /*!< Device name: SEMC */
#define BOARD_INITSDRAMPINS_SEMC_CKE_SIGNAL semc_cke /*!< SEMC signal: semc_cke */
/* GPIO_EMC_30 (number 126), SEMC_CLK/U14[38] */
#define BOARD_INITSDRAMPINS_SEMC_CLK_PERIPHERAL SEMC /*!< Device name: SEMC */
#define BOARD_INITSDRAMPINS_SEMC_CLK_SIGNAL semc_clk /*!< SEMC signal: semc_clk */
/* GPIO_EMC_12 (number 3), SEMC_CS0/U14[19] */
#define BOARD_INITSDRAMPINS_SEMC_CS0_PERIPHERAL SEMC /*!< Device name: SEMC */
#define BOARD_INITSDRAMPINS_SEMC_CS0_SIGNAL CS /*!< SEMC signal: CS */
#define BOARD_INITSDRAMPINS_SEMC_CS0_CHANNEL 0U /*!< SEMC CS channel: 0 */
/* GPIO_EMC_09 (number 8), SEMC_WE/U14[16] */
#define BOARD_INITSDRAMPINS_SEMC_WE_PERIPHERAL SEMC /*!< Device name: SEMC */
#define BOARD_INITSDRAMPINS_SEMC_WE_SIGNAL semc_we /*!< SEMC signal: semc_we */
/* GPIO_EMC_11 (number 4), SEMC_RAS/U14[18] */
#define BOARD_INITSDRAMPINS_SEMC_RAS_PERIPHERAL SEMC /*!< Device name: SEMC */
#define BOARD_INITSDRAMPINS_SEMC_RAS_SIGNAL semc_ras /*!< SEMC signal: semc_ras */
/* GPIO_EMC_28 (number 128), SAI3_MCLK */
#define BOARD_INITSDRAMPINS_SEMC_DQS_PERIPHERAL SEMC /*!< Device name: SEMC */
#define BOARD_INITSDRAMPINS_SEMC_DQS_SIGNAL semc_dqs /*!< SEMC signal: semc_dqs */
/* GPIO_EMC_31 (number 125), SEMC_DM1/U14[39] */
#define BOARD_INITSDRAMPINS_SEMC_DM1_PERIPHERAL SEMC /*!< Device name: SEMC */
#define BOARD_INITSDRAMPINS_SEMC_DM1_SIGNAL DM /*!< SEMC signal: DM */
#define BOARD_INITSDRAMPINS_SEMC_DM1_CHANNEL 1U /*!< SEMC DM channel: 1 */
/* GPIO_EMC_08 (number 9), SEMC_DM0/U14[15] */
#define BOARD_INITSDRAMPINS_SEMC_DM0_PERIPHERAL SEMC /*!< Device name: SEMC */
#define BOARD_INITSDRAMPINS_SEMC_DM0_SIGNAL DM /*!< SEMC signal: DM */
#define BOARD_INITSDRAMPINS_SEMC_DM0_CHANNEL 0U /*!< SEMC DM channel: 0 */
/* GPIO_EMC_39 (number 117), SEMC_D15/U14[53] */
#define BOARD_INITSDRAMPINS_SEMC_D15_PERIPHERAL SEMC /*!< Device name: SEMC */
#define BOARD_INITSDRAMPINS_SEMC_D15_SIGNAL DATA /*!< SEMC signal: DATA */
#define BOARD_INITSDRAMPINS_SEMC_D15_CHANNEL 15U /*!< SEMC DATA channel: 15 */
/* GPIO_EMC_38 (number 118), SEMC_D14/U14[51] */
#define BOARD_INITSDRAMPINS_SEMC_D14_PERIPHERAL SEMC /*!< Device name: SEMC */
#define BOARD_INITSDRAMPINS_SEMC_D14_SIGNAL DATA /*!< SEMC signal: DATA */
#define BOARD_INITSDRAMPINS_SEMC_D14_CHANNEL 14U /*!< SEMC DATA channel: 14 */
/* GPIO_EMC_37 (number 119), SEMC_D13/U14[50] */
#define BOARD_INITSDRAMPINS_SEMC_D13_PERIPHERAL SEMC /*!< Device name: SEMC */
#define BOARD_INITSDRAMPINS_SEMC_D13_SIGNAL DATA /*!< SEMC signal: DATA */
#define BOARD_INITSDRAMPINS_SEMC_D13_CHANNEL 13U /*!< SEMC DATA channel: 13 */
/* GPIO_EMC_36 (number 120), SEMC_D12/U14[48] */
#define BOARD_INITSDRAMPINS_SEMC_D12_PERIPHERAL SEMC /*!< Device name: SEMC */
#define BOARD_INITSDRAMPINS_SEMC_D12_SIGNAL DATA /*!< SEMC signal: DATA */
#define BOARD_INITSDRAMPINS_SEMC_D12_CHANNEL 12U /*!< SEMC DATA channel: 12 */
/* GPIO_EMC_34 (number 122), SEMC_D10/U14[45] */
#define BOARD_INITSDRAMPINS_SEMC_D10_PERIPHERAL SEMC /*!< Device name: SEMC */
#define BOARD_INITSDRAMPINS_SEMC_D10_SIGNAL DATA /*!< SEMC signal: DATA */
#define BOARD_INITSDRAMPINS_SEMC_D10_CHANNEL 10U /*!< SEMC DATA channel: 10 */
/* GPIO_EMC_35 (number 121), SEMC_D11/U14[47] */
#define BOARD_INITSDRAMPINS_SEMC_D11_PERIPHERAL SEMC /*!< Device name: SEMC */
#define BOARD_INITSDRAMPINS_SEMC_D11_SIGNAL DATA /*!< SEMC signal: DATA */
#define BOARD_INITSDRAMPINS_SEMC_D11_CHANNEL 11U /*!< SEMC DATA channel: 11 */
/* GPIO_EMC_33 (number 123), SEMC_D9/U14[44] */
#define BOARD_INITSDRAMPINS_SEMC_D9_PERIPHERAL SEMC /*!< Device name: SEMC */
#define BOARD_INITSDRAMPINS_SEMC_D9_SIGNAL DATA /*!< SEMC signal: DATA */
#define BOARD_INITSDRAMPINS_SEMC_D9_CHANNEL 9U /*!< SEMC DATA channel: 09 */
/* GPIO_EMC_32 (number 124), SEMC_D8/U14[42] */
#define BOARD_INITSDRAMPINS_SEMC_D8_PERIPHERAL SEMC /*!< Device name: SEMC */
#define BOARD_INITSDRAMPINS_SEMC_D8_SIGNAL DATA /*!< SEMC signal: DATA */
#define BOARD_INITSDRAMPINS_SEMC_D8_CHANNEL 8U /*!< SEMC DATA channel: 08 */
/* GPIO_EMC_07 (number 10), SEMC_D7/U14[13] */
#define BOARD_INITSDRAMPINS_SEMC_D7_PERIPHERAL SEMC /*!< Device name: SEMC */
#define BOARD_INITSDRAMPINS_SEMC_D7_SIGNAL DATA /*!< SEMC signal: DATA */
#define BOARD_INITSDRAMPINS_SEMC_D7_CHANNEL 7U /*!< SEMC DATA channel: 07 */
/* GPIO_EMC_06 (number 12), SEMC_D6/U14[11] */
#define BOARD_INITSDRAMPINS_SEMC_D6_PERIPHERAL SEMC /*!< Device name: SEMC */
#define BOARD_INITSDRAMPINS_SEMC_D6_SIGNAL DATA /*!< SEMC signal: DATA */
#define BOARD_INITSDRAMPINS_SEMC_D6_CHANNEL 6U /*!< SEMC DATA channel: 06 */
/* GPIO_EMC_05 (number 13), SEMC_D5/U14[10] */
#define BOARD_INITSDRAMPINS_SEMC_D5_PERIPHERAL SEMC /*!< Device name: SEMC */
#define BOARD_INITSDRAMPINS_SEMC_D5_SIGNAL DATA /*!< SEMC signal: DATA */
#define BOARD_INITSDRAMPINS_SEMC_D5_CHANNEL 5U /*!< SEMC DATA channel: 05 */
/* GPIO_EMC_04 (number 14), SEMC_D4/U14[8] */
#define BOARD_INITSDRAMPINS_SEMC_D4_PERIPHERAL SEMC /*!< Device name: SEMC */
#define BOARD_INITSDRAMPINS_SEMC_D4_SIGNAL DATA /*!< SEMC signal: DATA */
#define BOARD_INITSDRAMPINS_SEMC_D4_CHANNEL 4U /*!< SEMC DATA channel: 04 */
/* GPIO_EMC_03 (number 15), SEMC_D3/U14[7] */
#define BOARD_INITSDRAMPINS_SEMC_D3_PERIPHERAL SEMC /*!< Device name: SEMC */
#define BOARD_INITSDRAMPINS_SEMC_D3_SIGNAL DATA /*!< SEMC signal: DATA */
#define BOARD_INITSDRAMPINS_SEMC_D3_CHANNEL 3U /*!< SEMC DATA channel: 03 */
/* GPIO_EMC_02 (number 16), SEMC_D2/U14[5] */
#define BOARD_INITSDRAMPINS_SEMC_D2_PERIPHERAL SEMC /*!< Device name: SEMC */
#define BOARD_INITSDRAMPINS_SEMC_D2_SIGNAL DATA /*!< SEMC signal: DATA */
#define BOARD_INITSDRAMPINS_SEMC_D2_CHANNEL 2U /*!< SEMC DATA channel: 02 */
/* GPIO_EMC_01 (number 17), SEMC_D1/U14[4] */
#define BOARD_INITSDRAMPINS_SEMC_D1_PERIPHERAL SEMC /*!< Device name: SEMC */
#define BOARD_INITSDRAMPINS_SEMC_D1_SIGNAL DATA /*!< SEMC signal: DATA */
#define BOARD_INITSDRAMPINS_SEMC_D1_CHANNEL 1U /*!< SEMC DATA channel: 01 */
/* GPIO_EMC_00 (number 18), SEMC_D0/U14[2] */
#define BOARD_INITSDRAMPINS_SEMC_D0_PERIPHERAL SEMC /*!< Device name: SEMC */
#define BOARD_INITSDRAMPINS_SEMC_D0_SIGNAL DATA /*!< SEMC signal: DATA */
#define BOARD_INITSDRAMPINS_SEMC_D0_CHANNEL 0U /*!< SEMC DATA channel: 00 */
/*!
* @brief Configures pin routing and optionally pin electrical features.
*
*/
void BOARD_InitSDRAMPins(void);
/* GPIO_SD_B1_01 (number 32), CAN1_RX/U9[4] */
#define BOARD_INITCANPINS_CAN1_RX_PERIPHERAL CAN1 /*!< Device name: CAN1 */
#define BOARD_INITCANPINS_CAN1_RX_SIGNAL RX /*!< CAN1 signal: RX */
/* GPIO_SD_B1_00 (number 33), CAN1_TX/U9[1] */
#define BOARD_INITCANPINS_CAN1_TX_PERIPHERAL CAN1 /*!< Device name: CAN1 */
#define BOARD_INITCANPINS_CAN1_TX_SIGNAL TX /*!< CAN1 signal: TX */
/*!
* @brief Configures pin routing and optionally pin electrical features.
*
*/
void BOARD_InitCANPins(void);
/* GPIO_AD_B0_11 (number 97), ENET_CRS_DV/U11[18]/J19[6] */
#define BOARD_INITENETPINS_ENET_CRS_DV_PERIPHERAL ENET /*!< Device name: ENET */
#define BOARD_INITENETPINS_ENET_CRS_DV_SIGNAL enet_rx_en /*!< ENET signal: enet_rx_en */
/* GPIO_AD_B1_06 (number 84), ENET_INT/U11[21]/J17[16] */
#define BOARD_INITENETPINS_ENET_INT_GPIO GPIO1 /*!< GPIO device name: GPIO1 */
#define BOARD_INITENETPINS_ENET_INT_PORT GPIO1 /*!< PORT device name: GPIO1 */
#define BOARD_INITENETPINS_ENET_INT_PIN 22U /*!< GPIO1 pin index: 22 */
/* GPIO_AD_B0_04 (number 107), JTAG_TDO/ENET_RST/U11[32] */
#define BOARD_INITENETPINS_ENET_RST_GPIO GPIO1 /*!< GPIO device name: GPIO1 */
#define BOARD_INITENETPINS_ENET_RST_PORT GPIO1 /*!< PORT device name: GPIO1 */
#define BOARD_INITENETPINS_ENET_RST_PIN 4U /*!< GPIO1 pin index: 4 */
/* GPIO_AD_B0_08 (number 100), ENET_TX_REF_CLK/U11[9] */
#define BOARD_INITENETPINS_ENET_TX_CLK_PERIPHERAL ENET /*!< Device name: ENET */
#define BOARD_INITENETPINS_ENET_TX_CLK_SIGNAL enet_tx_clk /*!< ENET signal: enet_tx_clk */
/* GPIO_AD_B0_13 (number 95), ENET_TXEN/U11[23]/J19[10] */
#define BOARD_INITENETPINS_ENET_TXEN_PERIPHERAL ENET /*!< Device name: ENET */
#define BOARD_INITENETPINS_ENET_TXEN_SIGNAL enet_tx_en /*!< ENET signal: enet_tx_en */
/* GPIO_AD_B0_15 (number 93), ENET_TXD1/U11[25]/J19[4] */
#define BOARD_INITENETPINS_ENET_TXD1_PERIPHERAL ENET /*!< Device name: ENET */
#define BOARD_INITENETPINS_ENET_TXD1_SIGNAL enet_tx_data /*!< ENET signal: enet_tx_data */
#define BOARD_INITENETPINS_ENET_TXD1_CHANNEL 1U /*!< ENET enet_tx_data channel: 1 */
/* GPIO_AD_B0_14 (number 94), ENET_TXD0/U11[24]/J17[14] */
#define BOARD_INITENETPINS_ENET_TXD0_PERIPHERAL ENET /*!< Device name: ENET */
#define BOARD_INITENETPINS_ENET_TXD0_SIGNAL enet_tx_data /*!< ENET signal: enet_tx_data */
#define BOARD_INITENETPINS_ENET_TXD0_CHANNEL 0U /*!< ENET enet_tx_data channel: 0 */
/* GPIO_AD_B0_12 (number 96), ENET_RXER/U11[20]/J19[8] */
#define BOARD_INITENETPINS_ENET_RXER_PERIPHERAL ENET /*!< Device name: ENET */
#define BOARD_INITENETPINS_ENET_RXER_SIGNAL enet_rx_er /*!< ENET signal: enet_rx_er */
/* GPIO_AD_B0_09 (number 99), ENET_RXD1/U11[15]/J17[6] */
#define BOARD_INITENETPINS_ENET_RXD1_PERIPHERAL ENET /*!< Device name: ENET */
#define BOARD_INITENETPINS_ENET_RXD1_SIGNAL enet_rx_data /*!< ENET signal: enet_rx_data */
#define BOARD_INITENETPINS_ENET_RXD1_CHANNEL 1U /*!< ENET enet_rx_data channel: 1 */
/* GPIO_AD_B0_10 (number 98), ENET_RXD0/U11[16]/J19[12] */
#define BOARD_INITENETPINS_ENET_RXD0_PERIPHERAL ENET /*!< Device name: ENET */
#define BOARD_INITENETPINS_ENET_RXD0_SIGNAL enet_rx_data /*!< ENET signal: enet_rx_data */
#define BOARD_INITENETPINS_ENET_RXD0_CHANNEL 0U /*!< ENET enet_rx_data channel: 0 */
/* GPIO_EMC_40 (number 116), ENET_MDIO/U11[11] */
#define BOARD_INITENETPINS_ENET_MDIO_PERIPHERAL ENET /*!< Device name: ENET */
#define BOARD_INITENETPINS_ENET_MDIO_SIGNAL enet_mdio /*!< ENET signal: enet_mdio */
/* GPIO_EMC_41 (number 115), ENET_MDC/U11[12] */
#define BOARD_INITENETPINS_ENET_MDC_PERIPHERAL ENET /*!< Device name: ENET */
#define BOARD_INITENETPINS_ENET_MDC_SIGNAL enet_mdc /*!< ENET signal: enet_mdc */
/*!
* @brief Configures pin routing and optionally pin electrical features.
*
*/
void BOARD_InitENETPins(void);
/* GPIO_SD_B0_03 (number 45), SD1_CLK/J15[5] */
#define BOARD_INITUSDHCPINS_SD1_CLK_PERIPHERAL USDHC1 /*!< Device name: USDHC1 */
#define BOARD_INITUSDHCPINS_SD1_CLK_SIGNAL usdhc_clk /*!< USDHC1 signal: usdhc_clk */
/* GPIO_SD_B0_02 (number 46), SD1_CMD/J15[3] */
#define BOARD_INITUSDHCPINS_SD1_CMD_PERIPHERAL USDHC1 /*!< Device name: USDHC1 */
#define BOARD_INITUSDHCPINS_SD1_CMD_SIGNAL usdhc_cmd /*!< USDHC1 signal: usdhc_cmd */
/* GPIO_SD_B0_04 (number 43), SD1_D0/J15[7] */
#define BOARD_INITUSDHCPINS_SD1_D0_PERIPHERAL USDHC1 /*!< Device name: USDHC1 */
#define BOARD_INITUSDHCPINS_SD1_D0_SIGNAL usdhc_data /*!< USDHC1 signal: usdhc_data */
#define BOARD_INITUSDHCPINS_SD1_D0_CHANNEL 0U /*!< USDHC1 usdhc_data channel: 0 */
/* GPIO_SD_B0_05 (number 42), SD1_D1/J15[8] */
#define BOARD_INITUSDHCPINS_SD1_D1_PERIPHERAL USDHC1 /*!< Device name: USDHC1 */
#define BOARD_INITUSDHCPINS_SD1_D1_SIGNAL usdhc_data /*!< USDHC1 signal: usdhc_data */
#define BOARD_INITUSDHCPINS_SD1_D1_CHANNEL 1U /*!< USDHC1 usdhc_data channel: 1 */
/* GPIO_SD_B0_00 (number 48), SD1_D2/J15[1] */
#define BOARD_INITUSDHCPINS_SD1_D2_PERIPHERAL USDHC1 /*!< Device name: USDHC1 */
#define BOARD_INITUSDHCPINS_SD1_D2_SIGNAL usdhc_data /*!< USDHC1 signal: usdhc_data */
#define BOARD_INITUSDHCPINS_SD1_D2_CHANNEL 2U /*!< USDHC1 usdhc_data channel: 2 */
/* GPIO_SD_B0_01 (number 47), SD1_D3/J15[2] */
#define BOARD_INITUSDHCPINS_SD1_D3_PERIPHERAL USDHC1 /*!< Device name: USDHC1 */
#define BOARD_INITUSDHCPINS_SD1_D3_SIGNAL usdhc_data /*!< USDHC1 signal: usdhc_data */
#define BOARD_INITUSDHCPINS_SD1_D3_CHANNEL 3U /*!< USDHC1 usdhc_data channel: 3 */
/* GPIO_SD_B0_06 (number 41), SD_CD_SW/J15[9] */
#define BOARD_INITUSDHCPINS_SD_CD_SW_GPIO GPIO3 /*!< GPIO device name: GPIO3 */
#define BOARD_INITUSDHCPINS_SD_CD_SW_PORT GPIO3 /*!< PORT device name: GPIO3 */
#define BOARD_INITUSDHCPINS_SD_CD_SW_PIN 19U /*!< GPIO3 pin index: 19 */
/*!
* @brief Configures pin routing and optionally pin electrical features.
*
*/
void BOARD_InitUSDHCPins(void);
/* GPIO_SD_B1_07 (number 24), SAI3_TX_SYNC */
#define BOARD_INITQSPIPINS_FlexSPI_CLK_PERIPHERAL FLEXSPI /*!< Device name: FLEXSPI */
#define BOARD_INITQSPIPINS_FlexSPI_CLK_SIGNAL FLEXSPI_A_SCLK /*!< FLEXSPI signal: FLEXSPI_A_SCLK */
/* GPIO_SD_B1_08 (number 23), SAI3_TXD */
#define BOARD_INITQSPIPINS_FlexSPI_D0_A_PERIPHERAL FLEXSPI /*!< Device name: FLEXSPI */
#define BOARD_INITQSPIPINS_FlexSPI_D0_A_SIGNAL FLEXSPI_A_DATA0 /*!< FLEXSPI signal: FLEXSPI_A_DATA0 */
/* GPIO_SD_B1_10 (number 21), SD_PWREN */
#define BOARD_INITQSPIPINS_FlexSPI_D1_A_PERIPHERAL FLEXSPI /*!< Device name: FLEXSPI */
#define BOARD_INITQSPIPINS_FlexSPI_D1_A_SIGNAL FLEXSPI_A_DATA1 /*!< FLEXSPI signal: FLEXSPI_A_DATA1 */
/* GPIO_SD_B1_09 (number 22), AUD_INT */
#define BOARD_INITQSPIPINS_FlexSPI_D2_A_PERIPHERAL FLEXSPI /*!< Device name: FLEXSPI */
#define BOARD_INITQSPIPINS_FlexSPI_D2_A_SIGNAL FLEXSPI_A_DATA2 /*!< FLEXSPI signal: FLEXSPI_A_DATA2 */
/* GPIO_SD_B1_06 (number 25), SAI3_TX_BCLK */
#define BOARD_INITQSPIPINS_FlexSPI_D3_A_PERIPHERAL FLEXSPI /*!< Device name: FLEXSPI */
#define BOARD_INITQSPIPINS_FlexSPI_D3_A_SIGNAL FLEXSPI_A_DATA3 /*!< FLEXSPI signal: FLEXSPI_A_DATA3 */
/* GPIO_SD_B1_11 (number 19), SAI3_RXD */
#define BOARD_INITQSPIPINS_FlexSPI_SS0_PERIPHERAL FLEXSPI /*!< Device name: FLEXSPI */
#define BOARD_INITQSPIPINS_FlexSPI_SS0_SIGNAL FLEXSPI_A_SS0_B /*!< FLEXSPI signal: FLEXSPI_A_SS0_B */
/*!
* @brief Configures pin routing and optionally pin electrical features.
*
*/
void BOARD_InitQSPIPins(void);
#if defined(__cplusplus)
}
#endif
/*!
* @}
*/
#endif /* _PIN_MUX_H_ */
/***********************************************************************************************************************
* EOF
**********************************************************************************************************************/
components/espressif__tinyusb/hw/bsp/imxrt/boards/mimxrt1024_evk/evkmimxrt1024_flexspi_nor_config.c
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/*
* Copyright 2020 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include "evkmimxrt1024_flexspi_nor_config.h"
/* Component ID definition, used by tools. */
#ifndef FSL_COMPONENT_ID
#define FSL_COMPONENT_ID "platform.drivers.xip_board"
#endif
/*******************************************************************************
* Code
******************************************************************************/
#if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1)
#if defined(__CC_ARM) || defined(__ARMCC_VERSION) || defined(__GNUC__)
__attribute__((section(".boot_hdr.conf"), used))
#elif defined(__ICCARM__)
#pragma location = ".boot_hdr.conf"
#endif
const flexspi_nor_config_t qspiflash_config = {
.memConfig =
{
.tag = FLEXSPI_CFG_BLK_TAG,
.version = FLEXSPI_CFG_BLK_VERSION,
.readSampleClkSrc = kFlexSPIReadSampleClk_LoopbackInternally,
.csHoldTime = 3u,
.csSetupTime = 3u,
.sflashPadType = kSerialFlash_4Pads,
.serialClkFreq = kFlexSpiSerialClk_60MHz,
.sflashA1Size = 4u * 1024u * 1024u,
.lookupTable =
{
// Read LUTs
FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEB, RADDR_SDR, FLEXSPI_4PAD, 0x18),
FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 0x06, READ_SDR, FLEXSPI_4PAD, 0x04),
},
},
.pageSize = 256u,
.sectorSize = 4u * 1024u,
.blockSize = 64u * 1024u,
.isUniformBlockSize = false,
};
#endif /* XIP_BOOT_HEADER_ENABLE */
components/espressif__tinyusb/hw/bsp/imxrt/boards/mimxrt1024_evk/evkmimxrt1024_flexspi_nor_config.h
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/*
* Copyright 2020 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef __EVKMIMXRT1024_FLEXSPI_NOR_CONFIG__
#define __EVKMIMXRT1024_FLEXSPI_NOR_CONFIG__
#include <stdint.h>
#include <stdbool.h>
#include "fsl_common.h"
/*! @name Driver version */
/*@{*/
/*! @brief XIP_BOARD driver version 2.0.1. */
#define FSL_XIP_BOARD_DRIVER_VERSION (MAKE_VERSION(2, 0, 1))
/*@}*/
/* FLEXSPI memory config block related definitions */
#define FLEXSPI_CFG_BLK_TAG (0x42464346UL) // ascii "FCFB" Big Endian
#define FLEXSPI_CFG_BLK_VERSION (0x56010400UL) // V1.4.0
#define FLEXSPI_CFG_BLK_SIZE (512)
/* FLEXSPI Feature related definitions */
#define FLEXSPI_FEATURE_HAS_PARALLEL_MODE 1
/* Lookup table related definitions */
#define CMD_INDEX_READ 0
#define CMD_INDEX_READSTATUS 1
#define CMD_INDEX_WRITEENABLE 2
#define CMD_INDEX_WRITE 4
#define CMD_LUT_SEQ_IDX_READ 0
#define CMD_LUT_SEQ_IDX_READSTATUS 1
#define CMD_LUT_SEQ_IDX_WRITEENABLE 3
#define CMD_LUT_SEQ_IDX_WRITE 9
#define CMD_SDR 0x01
#define CMD_DDR 0x21
#define RADDR_SDR 0x02
#define RADDR_DDR 0x22
#define CADDR_SDR 0x03
#define CADDR_DDR 0x23
#define MODE1_SDR 0x04
#define MODE1_DDR 0x24
#define MODE2_SDR 0x05
#define MODE2_DDR 0x25
#define MODE4_SDR 0x06
#define MODE4_DDR 0x26
#define MODE8_SDR 0x07
#define MODE8_DDR 0x27
#define WRITE_SDR 0x08
#define WRITE_DDR 0x28
#define READ_SDR 0x09
#define READ_DDR 0x29
#define LEARN_SDR 0x0A
#define LEARN_DDR 0x2A
#define DATSZ_SDR 0x0B
#define DATSZ_DDR 0x2B
#define DUMMY_SDR 0x0C
#define DUMMY_DDR 0x2C
#define DUMMY_RWDS_SDR 0x0D
#define DUMMY_RWDS_DDR 0x2D
#define JMP_ON_CS 0x1F
#define STOP 0
#define FLEXSPI_1PAD 0
#define FLEXSPI_2PAD 1
#define FLEXSPI_4PAD 2
#define FLEXSPI_8PAD 3
#define FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) \
(FLEXSPI_LUT_OPERAND0(op0) | FLEXSPI_LUT_NUM_PADS0(pad0) | FLEXSPI_LUT_OPCODE0(cmd0) | FLEXSPI_LUT_OPERAND1(op1) | \
FLEXSPI_LUT_NUM_PADS1(pad1) | FLEXSPI_LUT_OPCODE1(cmd1))
//!@brief Definitions for FlexSPI Serial Clock Frequency
typedef enum _FlexSpiSerialClockFreq
{
kFlexSpiSerialClk_30MHz = 1,
kFlexSpiSerialClk_50MHz = 2,
kFlexSpiSerialClk_60MHz = 3,
kFlexSpiSerialClk_75MHz = 4,
kFlexSpiSerialClk_80MHz = 5,
kFlexSpiSerialClk_100MHz = 6,
kFlexSpiSerialClk_133MHz = 7,
} flexspi_serial_clk_freq_t;
//!@brief FlexSPI clock configuration type
enum
{
kFlexSpiClk_SDR, //!< Clock configure for SDR mode
kFlexSpiClk_DDR, //!< Clock configurat for DDR mode
};
//!@brief FlexSPI Read Sample Clock Source definition
typedef enum _FlashReadSampleClkSource
{
kFlexSPIReadSampleClk_LoopbackInternally = 0,
kFlexSPIReadSampleClk_LoopbackFromDqsPad = 1,
kFlexSPIReadSampleClk_LoopbackFromSckPad = 2,
kFlexSPIReadSampleClk_ExternalInputFromDqsPad = 3,
} flexspi_read_sample_clk_t;
//!@brief Misc feature bit definitions
enum
{
kFlexSpiMiscOffset_DiffClkEnable = 0, //!< Bit for Differential clock enable
kFlexSpiMiscOffset_Ck2Enable = 1, //!< Bit for CK2 enable
kFlexSpiMiscOffset_ParallelEnable = 2, //!< Bit for Parallel mode enable
kFlexSpiMiscOffset_WordAddressableEnable = 3, //!< Bit for Word Addressable enable
kFlexSpiMiscOffset_SafeConfigFreqEnable = 4, //!< Bit for Safe Configuration Frequency enable
kFlexSpiMiscOffset_PadSettingOverrideEnable = 5, //!< Bit for Pad setting override enable
kFlexSpiMiscOffset_DdrModeEnable = 6, //!< Bit for DDR clock confiuration indication.
};
//!@brief Flash Type Definition
enum
{
kFlexSpiDeviceType_SerialNOR = 1, //!< Flash devices are Serial NOR
kFlexSpiDeviceType_SerialNAND = 2, //!< Flash devices are Serial NAND
kFlexSpiDeviceType_SerialRAM = 3, //!< Flash devices are Serial RAM/HyperFLASH
kFlexSpiDeviceType_MCP_NOR_NAND = 0x12, //!< Flash device is MCP device, A1 is Serial NOR, A2 is Serial NAND
kFlexSpiDeviceType_MCP_NOR_RAM = 0x13, //!< Flash device is MCP device, A1 is Serial NOR, A2 is Serial RAMs
};
//!@brief Flash Pad Definitions
enum
{
kSerialFlash_1Pad = 1,
kSerialFlash_2Pads = 2,
kSerialFlash_4Pads = 4,
kSerialFlash_8Pads = 8,
};
//!@brief FlexSPI LUT Sequence structure
typedef struct _lut_sequence
{
uint8_t seqNum; //!< Sequence Number, valid number: 1-16
uint8_t seqId; //!< Sequence Index, valid number: 0-15
uint16_t reserved;
} flexspi_lut_seq_t;
//!@brief Flash Configuration Command Type
enum
{
kDeviceConfigCmdType_Generic, //!< Generic command, for example: configure dummy cycles, drive strength, etc
kDeviceConfigCmdType_QuadEnable, //!< Quad Enable command
kDeviceConfigCmdType_Spi2Xpi, //!< Switch from SPI to DPI/QPI/OPI mode
kDeviceConfigCmdType_Xpi2Spi, //!< Switch from DPI/QPI/OPI to SPI mode
kDeviceConfigCmdType_Spi2NoCmd, //!< Switch to 0-4-4/0-8-8 mode
kDeviceConfigCmdType_Reset, //!< Reset device command
};
//!@brief FlexSPI Memory Configuration Block
typedef struct _FlexSPIConfig
{
uint32_t tag; //!< [0x000-0x003] Tag, fixed value 0x42464346UL
uint32_t version; //!< [0x004-0x007] Version,[31:24] -'V', [23:16] - Major, [15:8] - Minor, [7:0] - bugfix
uint32_t reserved0; //!< [0x008-0x00b] Reserved for future use
uint8_t readSampleClkSrc; //!< [0x00c-0x00c] Read Sample Clock Source, valid value: 0/1/3
uint8_t csHoldTime; //!< [0x00d-0x00d] CS hold time, default value: 3
uint8_t csSetupTime; //!< [0x00e-0x00e] CS setup time, default value: 3
uint8_t columnAddressWidth; //!< [0x00f-0x00f] Column Address with, for HyperBus protocol, it is fixed to 3, For
//! Serial NAND, need to refer to datasheet
uint8_t deviceModeCfgEnable; //!< [0x010-0x010] Device Mode Configure enable flag, 1 - Enable, 0 - Disable
uint8_t deviceModeType; //!< [0x011-0x011] Specify the configuration command type:Quad Enable, DPI/QPI/OPI switch,
//! Generic configuration, etc.
uint16_t waitTimeCfgCommands; //!< [0x012-0x013] Wait time for all configuration commands, unit: 100us, Used for
//! DPI/QPI/OPI switch or reset command
flexspi_lut_seq_t deviceModeSeq; //!< [0x014-0x017] Device mode sequence info, [7:0] - LUT sequence id, [15:8] - LUt
//! sequence number, [31:16] Reserved
uint32_t deviceModeArg; //!< [0x018-0x01b] Argument/Parameter for device configuration
uint8_t configCmdEnable; //!< [0x01c-0x01c] Configure command Enable Flag, 1 - Enable, 0 - Disable
uint8_t configModeType[3]; //!< [0x01d-0x01f] Configure Mode Type, similar as deviceModeTpe
flexspi_lut_seq_t
configCmdSeqs[3]; //!< [0x020-0x02b] Sequence info for Device Configuration command, similar as deviceModeSeq
uint32_t reserved1; //!< [0x02c-0x02f] Reserved for future use
uint32_t configCmdArgs[3]; //!< [0x030-0x03b] Arguments/Parameters for device Configuration commands
uint32_t reserved2; //!< [0x03c-0x03f] Reserved for future use
uint32_t controllerMiscOption; //!< [0x040-0x043] Controller Misc Options, see Misc feature bit definitions for more
//! details
uint8_t deviceType; //!< [0x044-0x044] Device Type: See Flash Type Definition for more details
uint8_t sflashPadType; //!< [0x045-0x045] Serial Flash Pad Type: 1 - Single, 2 - Dual, 4 - Quad, 8 - Octal
uint8_t serialClkFreq; //!< [0x046-0x046] Serial Flash Frequency, device specific definitions, See System Boot
//! Chapter for more details
uint8_t lutCustomSeqEnable; //!< [0x047-0x047] LUT customization Enable, it is required if the program/erase cannot
//! be done using 1 LUT sequence, currently, only applicable to HyperFLASH
uint32_t reserved3[2]; //!< [0x048-0x04f] Reserved for future use
uint32_t sflashA1Size; //!< [0x050-0x053] Size of Flash connected to A1
uint32_t sflashA2Size; //!< [0x054-0x057] Size of Flash connected to A2
uint32_t sflashB1Size; //!< [0x058-0x05b] Size of Flash connected to B1
uint32_t sflashB2Size; //!< [0x05c-0x05f] Size of Flash connected to B2
uint32_t csPadSettingOverride; //!< [0x060-0x063] CS pad setting override value
uint32_t sclkPadSettingOverride; //!< [0x064-0x067] SCK pad setting override value
uint32_t dataPadSettingOverride; //!< [0x068-0x06b] data pad setting override value
uint32_t dqsPadSettingOverride; //!< [0x06c-0x06f] DQS pad setting override value
uint32_t timeoutInMs; //!< [0x070-0x073] Timeout threshold for read status command
uint32_t commandInterval; //!< [0x074-0x077] CS deselect interval between two commands
uint16_t dataValidTime[2]; //!< [0x078-0x07b] CLK edge to data valid time for PORT A and PORT B, in terms of 0.1ns
uint16_t busyOffset; //!< [0x07c-0x07d] Busy offset, valid value: 0-31
uint16_t busyBitPolarity; //!< [0x07e-0x07f] Busy flag polarity, 0 - busy flag is 1 when flash device is busy, 1 -
//! busy flag is 0 when flash device is busy
uint32_t lookupTable[64]; //!< [0x080-0x17f] Lookup table holds Flash command sequences
flexspi_lut_seq_t lutCustomSeq[12]; //!< [0x180-0x1af] Customizable LUT Sequences
uint32_t reserved4[4]; //!< [0x1b0-0x1bf] Reserved for future use
} flexspi_mem_config_t;
/* */
#define NOR_CMD_INDEX_READ CMD_INDEX_READ //!< 0
#define NOR_CMD_INDEX_READSTATUS CMD_INDEX_READSTATUS //!< 1
#define NOR_CMD_INDEX_WRITEENABLE CMD_INDEX_WRITEENABLE //!< 2
#define NOR_CMD_INDEX_ERASESECTOR 3 //!< 3
#define NOR_CMD_INDEX_PAGEPROGRAM CMD_INDEX_WRITE //!< 4
#define NOR_CMD_INDEX_CHIPERASE 5 //!< 5
#define NOR_CMD_INDEX_DUMMY 6 //!< 6
#define NOR_CMD_INDEX_ERASEBLOCK 7 //!< 7
#define NOR_CMD_LUT_SEQ_IDX_READ CMD_LUT_SEQ_IDX_READ //!< 0 READ LUT sequence id in lookupTable stored in config block
#define NOR_CMD_LUT_SEQ_IDX_READSTATUS \
CMD_LUT_SEQ_IDX_READSTATUS //!< 1 Read Status LUT sequence id in lookupTable stored in config block
#define NOR_CMD_LUT_SEQ_IDX_READSTATUS_XPI \
2 //!< 2 Read status DPI/QPI/OPI sequence id in lookupTable stored in config block
#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE \
CMD_LUT_SEQ_IDX_WRITEENABLE //!< 3 Write Enable sequence id in lookupTable stored in config block
#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE_XPI \
4 //!< 4 Write Enable DPI/QPI/OPI sequence id in lookupTable stored in config block
#define NOR_CMD_LUT_SEQ_IDX_ERASESECTOR 5 //!< 5 Erase Sector sequence id in lookupTable stored in config block
#define NOR_CMD_LUT_SEQ_IDX_ERASEBLOCK 8 //!< 8 Erase Block sequence id in lookupTable stored in config block
#define NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM \
CMD_LUT_SEQ_IDX_WRITE //!< 9 Program sequence id in lookupTable stored in config block
#define NOR_CMD_LUT_SEQ_IDX_CHIPERASE 11 //!< 11 Chip Erase sequence in lookupTable id stored in config block
#define NOR_CMD_LUT_SEQ_IDX_READ_SFDP 13 //!< 13 Read SFDP sequence in lookupTable id stored in config block
#define NOR_CMD_LUT_SEQ_IDX_RESTORE_NOCMD \
14 //!< 14 Restore 0-4-4/0-8-8 mode sequence id in lookupTable stored in config block
#define NOR_CMD_LUT_SEQ_IDX_EXIT_NOCMD \
15 //!< 15 Exit 0-4-4/0-8-8 mode sequence id in lookupTable stored in config blobk
/*
* Serial NOR configuration block
*/
typedef struct _flexspi_nor_config
{
flexspi_mem_config_t memConfig; //!< Common memory configuration info via FlexSPI
uint32_t pageSize; //!< Page size of Serial NOR
uint32_t sectorSize; //!< Sector size of Serial NOR
uint8_t ipcmdSerialClkFreq; //!< Clock frequency for IP command
uint8_t isUniformBlockSize; //!< Sector/Block size is the same
uint8_t reserved0[2]; //!< Reserved for future use
uint8_t serialNorType; //!< Serial NOR Flash type: 0/1/2/3
uint8_t needExitNoCmdMode; //!< Need to exit NoCmd mode before other IP command
uint8_t halfClkForNonReadCmd; //!< Half the Serial Clock for non-read command: true/false
uint8_t needRestoreNoCmdMode; //!< Need to Restore NoCmd mode after IP command execution
uint32_t blockSize; //!< Block size
uint32_t reserve2[11]; //!< Reserved for future use
} flexspi_nor_config_t;
#ifdef __cplusplus
extern "C" {
#endif
#ifdef __cplusplus
}
#endif
#endif /* __EVKMIMXRT1024_FLEXSPI_NOR_CONFIG__ */
components/espressif__tinyusb/hw/bsp/imxrt/boards/mimxrt1024_evk/mimxrt1024_evk.mex
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<?xml version="1.0" encoding= "UTF-8" ?>
<configuration name="MIMXRT1024-EVK" xsi:schemaLocation="http://mcuxpresso.nxp.com/XSD/mex_configuration_13 http://mcuxpresso.nxp.com/XSD/mex_configuration_13.xsd" uuid="a558cc6e-82c2-41f9-9f55-0348efc7896f" version="13" xmlns="http://mcuxpresso.nxp.com/XSD/mex_configuration_13" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
<common>
<processor>MIMXRT1024xxxxx</processor>
<package>MIMXRT1024DAG5A</package>
<board>MIMXRT1024-EVK</board>
<board_revision>B1</board_revision>
<mcu_data>ksdk2_0</mcu_data>
<cores selected="core0">
<core name="Cortex-M7F" id="core0" description="M7 core"/>
</cores>
<description></description>
</common>
<preferences>
<validate_boot_init_only>false</validate_boot_init_only>
<generate_extended_information>false</generate_extended_information>
<generate_code_modified_registers_only>false</generate_code_modified_registers_only>
<update_include_paths>true</update_include_paths>
<generate_registers_defines>false</generate_registers_defines>
</preferences>
<tools>
<pins name="Pins" version="13.1" enabled="true" update_project_code="true">
<generated_project_files>
<file path="board/pin_mux.c" update_enabled="true"/>
<file path="board/pin_mux.h" update_enabled="true"/>
</generated_project_files>
<pins_profile>
<processor_version>13.0.2</processor_version>
<pin_labels>
<pin_label pin_num="52" pin_signal="WAKEUP" label="USER_BUTTON" identifier="USER_BUTTON"/>
<pin_label pin_num="82" pin_signal="GPIO_AD_B1_08" label="UART_TX/USER_LED/J17[4]" identifier="USER_LED"/>
</pin_labels>
<power_domains>
<power_domain name="NVCC_GPIO" value="3.3"/>
</power_domains>
</pins_profile>
<functions_list>
<function name="BOARD_InitPins">
<description>Configures pin routing and optionally pin electrical features.</description>
<options>
<callFromInitBoot>true</callFromInitBoot>
<coreID>core0</coreID>
<enableClock>true</enableClock>
</options>
<dependencies>
<dependency resourceType="Peripheral" resourceId="GPIO5" description="Peripheral GPIO5 is not initialized" problem_level="1" source="Pins:BOARD_InitPins">
<feature name="initialized" evaluation="equal">
<data>true</data>
</feature>
</dependency>
<dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitPins">
<feature name="enabled" evaluation="equal" configuration="core0">
<data>true</data>
</feature>
</dependency>
<dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Pins initialization requires the IOMUXC Driver in the project." problem_level="2" source="Pins:BOARD_InitPins">
<feature name="enabled" evaluation="equal" configuration="core0">
<data>true</data>
</feature>
</dependency>
<dependency resourceType="SWComponent" resourceId="platform.drivers.igpio" description="Pins initialization requires the IGPIO Driver in the project." problem_level="2" source="Pins:BOARD_InitPins">
<feature name="enabled" evaluation="equal" configuration="core0">
<data>true</data>
</feature>
</dependency>
</dependencies>
<pins>
<pin peripheral="GPIO5" signal="gpio_io, 00" pin_num="52" pin_signal="WAKEUP">
<pin_features>
<pin_feature name="direction" value="INPUT"/>
</pin_features>
</pin>
<pin peripheral="GPIO1" signal="gpio_io, 24" pin_num="82" pin_signal="GPIO_AD_B1_08">
<pin_features>
<pin_feature name="direction" value="OUTPUT"/>
</pin_features>
</pin>
</pins>
</function>
<function name="BOARD_InitDEBUG_UARTPins">
<description>Configures pin routing and optionally pin electrical features.</description>
<options>
<callFromInitBoot>true</callFromInitBoot>
<coreID>core0</coreID>
<enableClock>true</enableClock>
</options>
<dependencies>
<dependency resourceType="Peripheral" resourceId="LPUART1" description="Peripheral LPUART1 is not initialized" problem_level="1" source="Pins:BOARD_InitDEBUG_UARTPins">
<feature name="initialized" evaluation="equal">
<data>true</data>
</feature>
</dependency>
<dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitDEBUG_UARTPins">
<feature name="enabled" evaluation="equal" configuration="core0">
<data>true</data>
</feature>
</dependency>
<dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Pins initialization requires the IOMUXC Driver in the project." problem_level="2" source="Pins:BOARD_InitDEBUG_UARTPins">
<feature name="enabled" evaluation="equal" configuration="core0">
<data>true</data>
</feature>
</dependency>
</dependencies>
<pins>
<pin peripheral="LPUART1" signal="RX" pin_num="101" pin_signal="GPIO_AD_B0_07"/>
<pin peripheral="LPUART1" signal="TX" pin_num="105" pin_signal="GPIO_AD_B0_06"/>
</pins>
</function>
<function name="BOARD_InitSDRAMPins">
<description>Configures pin routing and optionally pin electrical features.</description>
<options>
<coreID>core0</coreID>
<enableClock>true</enableClock>
</options>
<dependencies>
<dependency resourceType="Peripheral" resourceId="SEMC" description="Peripheral SEMC is not initialized" problem_level="1" source="Pins:BOARD_InitSDRAMPins">
<feature name="initialized" evaluation="equal">
<data>true</data>
</feature>
</dependency>
<dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitSDRAMPins">
<feature name="enabled" evaluation="equal" configuration="core0">
<data>true</data>
</feature>
</dependency>
<dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Pins initialization requires the IOMUXC Driver in the project." problem_level="2" source="Pins:BOARD_InitSDRAMPins">
<feature name="enabled" evaluation="equal" configuration="core0">
<data>true</data>
</feature>
</dependency>
</dependencies>
<pins>
<pin peripheral="SEMC" signal="ADDR, 00" pin_num="142" pin_signal="GPIO_EMC_16"/>
<pin peripheral="SEMC" signal="ADDR, 01" pin_num="141" pin_signal="GPIO_EMC_17"/>
<pin peripheral="SEMC" signal="ADDR, 02" pin_num="140" pin_signal="GPIO_EMC_18"/>
<pin peripheral="SEMC" signal="ADDR, 03" pin_num="139" pin_signal="GPIO_EMC_19"/>
<pin peripheral="SEMC" signal="ADDR, 04" pin_num="138" pin_signal="GPIO_EMC_20"/>
<pin peripheral="SEMC" signal="ADDR, 06" pin_num="136" pin_signal="GPIO_EMC_22"/>
<pin peripheral="SEMC" signal="ADDR, 05" pin_num="137" pin_signal="GPIO_EMC_21"/>
<pin peripheral="SEMC" signal="ADDR, 07" pin_num="133" pin_signal="GPIO_EMC_23"/>
<pin peripheral="SEMC" signal="ADDR, 08" pin_num="132" pin_signal="GPIO_EMC_24"/>
<pin peripheral="SEMC" signal="ADDR, 09" pin_num="131" pin_signal="GPIO_EMC_25"/>
<pin peripheral="SEMC" signal="ADDR, 10" pin_num="143" pin_signal="GPIO_EMC_15"/>
<pin peripheral="SEMC" signal="ADDR, 11" pin_num="130" pin_signal="GPIO_EMC_26"/>
<pin peripheral="SEMC" signal="ADDR, 12" pin_num="129" pin_signal="GPIO_EMC_27"/>
<pin peripheral="SEMC" signal="BA, 0" pin_num="2" pin_signal="GPIO_EMC_13"/>
<pin peripheral="SEMC" signal="BA, 1" pin_num="1" pin_signal="GPIO_EMC_14"/>
<pin peripheral="SEMC" signal="semc_cas" pin_num="7" pin_signal="GPIO_EMC_10"/>
<pin peripheral="SEMC" signal="semc_cke" pin_num="127" pin_signal="GPIO_EMC_29"/>
<pin peripheral="SEMC" signal="semc_clk" pin_num="126" pin_signal="GPIO_EMC_30"/>
<pin peripheral="SEMC" signal="CS, 0" pin_num="3" pin_signal="GPIO_EMC_12"/>
<pin peripheral="SEMC" signal="semc_we" pin_num="8" pin_signal="GPIO_EMC_09"/>
<pin peripheral="SEMC" signal="semc_ras" pin_num="4" pin_signal="GPIO_EMC_11"/>
<pin peripheral="SEMC" signal="semc_dqs" pin_num="128" pin_signal="GPIO_EMC_28"/>
<pin peripheral="SEMC" signal="DM, 1" pin_num="125" pin_signal="GPIO_EMC_31"/>
<pin peripheral="SEMC" signal="DM, 0" pin_num="9" pin_signal="GPIO_EMC_08"/>
<pin peripheral="SEMC" signal="DATA, 15" pin_num="117" pin_signal="GPIO_EMC_39"/>
<pin peripheral="SEMC" signal="DATA, 14" pin_num="118" pin_signal="GPIO_EMC_38"/>
<pin peripheral="SEMC" signal="DATA, 13" pin_num="119" pin_signal="GPIO_EMC_37"/>
<pin peripheral="SEMC" signal="DATA, 12" pin_num="120" pin_signal="GPIO_EMC_36"/>
<pin peripheral="SEMC" signal="DATA, 10" pin_num="122" pin_signal="GPIO_EMC_34"/>
<pin peripheral="SEMC" signal="DATA, 11" pin_num="121" pin_signal="GPIO_EMC_35"/>
<pin peripheral="SEMC" signal="DATA, 09" pin_num="123" pin_signal="GPIO_EMC_33"/>
<pin peripheral="SEMC" signal="DATA, 08" pin_num="124" pin_signal="GPIO_EMC_32"/>
<pin peripheral="SEMC" signal="DATA, 07" pin_num="10" pin_signal="GPIO_EMC_07"/>
<pin peripheral="SEMC" signal="DATA, 06" pin_num="12" pin_signal="GPIO_EMC_06"/>
<pin peripheral="SEMC" signal="DATA, 05" pin_num="13" pin_signal="GPIO_EMC_05"/>
<pin peripheral="SEMC" signal="DATA, 04" pin_num="14" pin_signal="GPIO_EMC_04"/>
<pin peripheral="SEMC" signal="DATA, 03" pin_num="15" pin_signal="GPIO_EMC_03"/>
<pin peripheral="SEMC" signal="DATA, 02" pin_num="16" pin_signal="GPIO_EMC_02"/>
<pin peripheral="SEMC" signal="DATA, 01" pin_num="17" pin_signal="GPIO_EMC_01"/>
<pin peripheral="SEMC" signal="DATA, 00" pin_num="18" pin_signal="GPIO_EMC_00"/>
</pins>
</function>
<function name="BOARD_InitCANPins">
<description>Configures pin routing and optionally pin electrical features.</description>
<options>
<coreID>core0</coreID>
<enableClock>true</enableClock>
</options>
<dependencies>
<dependency resourceType="Peripheral" resourceId="CAN1" description="Peripheral CAN1 is not initialized" problem_level="1" source="Pins:BOARD_InitCANPins">
<feature name="initialized" evaluation="equal">
<data>true</data>
</feature>
</dependency>
<dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitCANPins">
<feature name="enabled" evaluation="equal" configuration="core0">
<data>true</data>
</feature>
</dependency>
<dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Pins initialization requires the IOMUXC Driver in the project." problem_level="2" source="Pins:BOARD_InitCANPins">
<feature name="enabled" evaluation="equal" configuration="core0">
<data>true</data>
</feature>
</dependency>
</dependencies>
<pins>
<pin peripheral="CAN1" signal="RX" pin_num="32" pin_signal="GPIO_SD_B1_01"/>
<pin peripheral="CAN1" signal="TX" pin_num="33" pin_signal="GPIO_SD_B1_00"/>
</pins>
</function>
<function name="BOARD_InitENETPins">
<description>Configures pin routing and optionally pin electrical features.</description>
<options>
<coreID>core0</coreID>
<enableClock>true</enableClock>
</options>
<dependencies>
<dependency resourceType="Peripheral" resourceId="ENET" description="Peripheral ENET is not initialized" problem_level="1" source="Pins:BOARD_InitENETPins">
<feature name="initialized" evaluation="equal">
<data>true</data>
</feature>
</dependency>
<dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitENETPins">
<feature name="enabled" evaluation="equal" configuration="core0">
<data>true</data>
</feature>
</dependency>
<dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Pins initialization requires the IOMUXC Driver in the project." problem_level="2" source="Pins:BOARD_InitENETPins">
<feature name="enabled" evaluation="equal" configuration="core0">
<data>true</data>
</feature>
</dependency>
</dependencies>
<pins>
<pin peripheral="ENET" signal="enet_rx_en" pin_num="97" pin_signal="GPIO_AD_B0_11"/>
<pin peripheral="GPIO1" signal="gpio_io, 22" pin_num="84" pin_signal="GPIO_AD_B1_06"/>
<pin peripheral="GPIO1" signal="gpio_io, 04" pin_num="107" pin_signal="GPIO_AD_B0_04"/>
<pin peripheral="ENET" signal="enet_tx_clk" pin_num="100" pin_signal="GPIO_AD_B0_08"/>
<pin peripheral="ENET" signal="enet_tx_en" pin_num="95" pin_signal="GPIO_AD_B0_13"/>
<pin peripheral="ENET" signal="enet_tx_data, 1" pin_num="93" pin_signal="GPIO_AD_B0_15"/>
<pin peripheral="ENET" signal="enet_tx_data, 0" pin_num="94" pin_signal="GPIO_AD_B0_14"/>
<pin peripheral="ENET" signal="enet_rx_er" pin_num="96" pin_signal="GPIO_AD_B0_12"/>
<pin peripheral="ENET" signal="enet_rx_data, 1" pin_num="99" pin_signal="GPIO_AD_B0_09"/>
<pin peripheral="ENET" signal="enet_rx_data, 0" pin_num="98" pin_signal="GPIO_AD_B0_10"/>
<pin peripheral="ENET" signal="enet_mdio" pin_num="116" pin_signal="GPIO_EMC_40"/>
<pin peripheral="ENET" signal="enet_mdc" pin_num="115" pin_signal="GPIO_EMC_41"/>
</pins>
</function>
<function name="BOARD_InitUSDHCPins">
<description>Configures pin routing and optionally pin electrical features.</description>
<options>
<coreID>core0</coreID>
<enableClock>true</enableClock>
</options>
<dependencies>
<dependency resourceType="Peripheral" resourceId="USDHC1" description="Peripheral USDHC1 is not initialized" problem_level="1" source="Pins:BOARD_InitUSDHCPins">
<feature name="initialized" evaluation="equal">
<data>true</data>
</feature>
</dependency>
<dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitUSDHCPins">
<feature name="enabled" evaluation="equal" configuration="core0">
<data>true</data>
</feature>
</dependency>
<dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Pins initialization requires the IOMUXC Driver in the project." problem_level="2" source="Pins:BOARD_InitUSDHCPins">
<feature name="enabled" evaluation="equal" configuration="core0">
<data>true</data>
</feature>
</dependency>
</dependencies>
<pins>
<pin peripheral="USDHC1" signal="usdhc_clk" pin_num="45" pin_signal="GPIO_SD_B0_03"/>
<pin peripheral="USDHC1" signal="usdhc_cmd" pin_num="46" pin_signal="GPIO_SD_B0_02"/>
<pin peripheral="USDHC1" signal="usdhc_data, 0" pin_num="43" pin_signal="GPIO_SD_B0_04"/>
<pin peripheral="USDHC1" signal="usdhc_data, 1" pin_num="42" pin_signal="GPIO_SD_B0_05"/>
<pin peripheral="USDHC1" signal="usdhc_data, 2" pin_num="48" pin_signal="GPIO_SD_B0_00"/>
<pin peripheral="USDHC1" signal="usdhc_data, 3" pin_num="47" pin_signal="GPIO_SD_B0_01"/>
<pin peripheral="GPIO3" signal="gpio_io, 19" pin_num="41" pin_signal="GPIO_SD_B0_06"/>
</pins>
</function>
<function name="BOARD_InitQSPIPins">
<description>Configures pin routing and optionally pin electrical features.</description>
<options>
<coreID>core0</coreID>
<enableClock>true</enableClock>
</options>
<dependencies>
<dependency resourceType="Peripheral" resourceId="FLEXSPI" description="Peripheral FLEXSPI is not initialized" problem_level="1" source="Pins:BOARD_InitQSPIPins">
<feature name="initialized" evaluation="equal">
<data>true</data>
</feature>
</dependency>
<dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitQSPIPins">
<feature name="enabled" evaluation="equal" configuration="core0">
<data>true</data>
</feature>
</dependency>
<dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Pins initialization requires the IOMUXC Driver in the project." problem_level="2" source="Pins:BOARD_InitQSPIPins">
<feature name="enabled" evaluation="equal" configuration="core0">
<data>true</data>
</feature>
</dependency>
</dependencies>
<pins>
<pin peripheral="FLEXSPI" signal="FLEXSPI_A_SCLK" pin_num="24" pin_signal="GPIO_SD_B1_07"/>
<pin peripheral="FLEXSPI" signal="FLEXSPI_A_DATA0" pin_num="23" pin_signal="GPIO_SD_B1_08"/>
<pin peripheral="FLEXSPI" signal="FLEXSPI_A_DATA1" pin_num="21" pin_signal="GPIO_SD_B1_10"/>
<pin peripheral="FLEXSPI" signal="FLEXSPI_A_DATA2" pin_num="22" pin_signal="GPIO_SD_B1_09"/>
<pin peripheral="FLEXSPI" signal="FLEXSPI_A_DATA3" pin_num="25" pin_signal="GPIO_SD_B1_06"/>
<pin peripheral="FLEXSPI" signal="FLEXSPI_A_SS0_B" pin_num="19" pin_signal="GPIO_SD_B1_11"/>
</pins>
</function>
</functions_list>
</pins>
<clocks name="Clocks" version="11.0" enabled="true" update_project_code="true">
<generated_project_files>
<file path="board/clock_config.c" update_enabled="true"/>
<file path="board/clock_config.h" update_enabled="true"/>
</generated_project_files>
<clocks_profile>
<processor_version>13.0.2</processor_version>
</clocks_profile>
<clock_configurations>
<clock_configuration name="BOARD_BootClockRUN" id_prefix="" prefix_user_defined="false">
<description></description>
<options/>
<dependencies>
<dependency resourceType="PinSignal" resourceId="XTALOSC24M.rtc_xtali" description="&apos;RTC_XTALI&apos; (Pins tool id: XTALOSC24M.rtc_xtali, Clocks tool id: XTALOSC24M.RTC_XTALI) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockRUN">
<feature name="routed" evaluation="">
<data>true</data>
</feature>
</dependency>
<dependency resourceType="PinSignal" resourceId="XTALOSC24M.rtc_xtali" description="&apos;RTC_XTALI&apos; (Pins tool id: XTALOSC24M.rtc_xtali, Clocks tool id: XTALOSC24M.RTC_XTALI) needs to have &apos;INPUT&apos; direction" problem_level="1" source="Clocks:BOARD_BootClockRUN">
<feature name="direction" evaluation="">
<data>INPUT</data>
</feature>
</dependency>
<dependency resourceType="PinSignal" resourceId="XTALOSC24M.rtc_xtalo" description="&apos;RTC_XTALO&apos; (Pins tool id: XTALOSC24M.rtc_xtalo, Clocks tool id: XTALOSC24M.RTC_XTALO) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockRUN">
<feature name="routed" evaluation="">
<data>true</data>
</feature>
</dependency>
<dependency resourceType="PinSignal" resourceId="XTALOSC24M.rtc_xtalo" description="&apos;RTC_XTALO&apos; (Pins tool id: XTALOSC24M.rtc_xtalo, Clocks tool id: XTALOSC24M.RTC_XTALO) needs to have &apos;OUTPUT&apos; direction" problem_level="1" source="Clocks:BOARD_BootClockRUN">
<feature name="direction" evaluation="">
<data>OUTPUT</data>
</feature>
</dependency>
<dependency resourceType="PinSignal" resourceId="XTALOSC24M.xtali" description="&apos;XTALI&apos; (Pins tool id: XTALOSC24M.xtali, Clocks tool id: XTALOSC24M.XTALI) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockRUN">
<feature name="routed" evaluation="">
<data>true</data>
</feature>
</dependency>
<dependency resourceType="PinSignal" resourceId="XTALOSC24M.xtali" description="&apos;XTALI&apos; (Pins tool id: XTALOSC24M.xtali, Clocks tool id: XTALOSC24M.XTALI) needs to have &apos;INPUT&apos; direction" problem_level="1" source="Clocks:BOARD_BootClockRUN">
<feature name="direction" evaluation="">
<data>INPUT</data>
</feature>
</dependency>
<dependency resourceType="PinSignal" resourceId="XTALOSC24M.xtalo" description="&apos;XTALO&apos; (Pins tool id: XTALOSC24M.xtalo, Clocks tool id: XTALOSC24M.XTALO) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockRUN">
<feature name="routed" evaluation="">
<data>true</data>
</feature>
</dependency>
<dependency resourceType="PinSignal" resourceId="XTALOSC24M.xtalo" description="&apos;XTALO&apos; (Pins tool id: XTALOSC24M.xtalo, Clocks tool id: XTALOSC24M.XTALO) needs to have &apos;OUTPUT&apos; direction" problem_level="1" source="Clocks:BOARD_BootClockRUN">
<feature name="direction" evaluation="">
<data>OUTPUT</data>
</feature>
</dependency>
<dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Clocks initialization requires the COMMON Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockRUN">
<feature name="enabled" evaluation="equal" configuration="core0">
<data>true</data>
</feature>
</dependency>
<dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Clocks initialization requires the IOMUXC Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockRUN">
<feature name="enabled" evaluation="equal" configuration="core0">
<data>true</data>
</feature>
</dependency>
</dependencies>
<clock_sources>
<clock_source id="XTALOSC24M.RTC_OSC.outFreq" value="32.768 kHz" locked="false" enabled="true"/>
</clock_sources>
<clock_outputs>
<clock_output id="AHB_CLK_ROOT.outFreq" value="500 MHz" locked="false" accuracy=""/>
<clock_output id="CAN_CLK_ROOT.outFreq" value="40 MHz" locked="false" accuracy=""/>
<clock_output id="CKIL_SYNC_CLK_ROOT.outFreq" value="32.768 kHz" locked="false" accuracy=""/>
<clock_output id="CLK_1M.outFreq" value="1 MHz" locked="false" accuracy=""/>
<clock_output id="CLK_24M.outFreq" value="24 MHz" locked="false" accuracy=""/>
<clock_output id="ENET_500M_REF_CLK.outFreq" value="500 MHz" locked="false" accuracy=""/>
<clock_output id="FLEXIO1_CLK_ROOT.outFreq" value="30 MHz" locked="false" accuracy=""/>
<clock_output id="FLEXSPI_CLK_ROOT.outFreq" value="132 MHz" locked="false" accuracy=""/>
<clock_output id="GPT1_ipg_clk_highfreq.outFreq" value="62.5 MHz" locked="false" accuracy=""/>
<clock_output id="GPT2_ipg_clk_highfreq.outFreq" value="62.5 MHz" locked="false" accuracy=""/>
<clock_output id="IPG_CLK_ROOT.outFreq" value="125 MHz" locked="false" accuracy=""/>
<clock_output id="LPI2C_CLK_ROOT.outFreq" value="60 MHz" locked="false" accuracy=""/>
<clock_output id="LPSPI_CLK_ROOT.outFreq" value="105.6 MHz" locked="false" accuracy=""/>
<clock_output id="MQS_MCLK.outFreq" value="1080/17 MHz" locked="false" accuracy=""/>
<clock_output id="PERCLK_CLK_ROOT.outFreq" value="62.5 MHz" locked="false" accuracy=""/>
<clock_output id="SAI1_CLK_ROOT.outFreq" value="1080/17 MHz" locked="false" accuracy=""/>
<clock_output id="SAI1_MCLK1.outFreq" value="1080/17 MHz" locked="false" accuracy=""/>
<clock_output id="SAI1_MCLK2.outFreq" value="1080/17 MHz" locked="false" accuracy=""/>
<clock_output id="SAI1_MCLK3.outFreq" value="30 MHz" locked="false" accuracy=""/>
<clock_output id="SAI2_CLK_ROOT.outFreq" value="1080/17 MHz" locked="false" accuracy=""/>
<clock_output id="SAI2_MCLK1.outFreq" value="1080/17 MHz" locked="false" accuracy=""/>
<clock_output id="SAI2_MCLK3.outFreq" value="30 MHz" locked="false" accuracy=""/>
<clock_output id="SAI3_CLK_ROOT.outFreq" value="1080/17 MHz" locked="false" accuracy=""/>
<clock_output id="SAI3_MCLK1.outFreq" value="1080/17 MHz" locked="false" accuracy=""/>
<clock_output id="SAI3_MCLK3.outFreq" value="30 MHz" locked="false" accuracy=""/>
<clock_output id="SEMC_CLK_ROOT.outFreq" value="62.5 MHz" locked="false" accuracy=""/>
<clock_output id="SPDIF0_CLK_ROOT.outFreq" value="30 MHz" locked="false" accuracy=""/>
<clock_output id="TRACE_CLK_ROOT.outFreq" value="132 MHz" locked="false" accuracy=""/>
<clock_output id="UART_CLK_ROOT.outFreq" value="80 MHz" locked="false" accuracy=""/>
<clock_output id="USBPHY1_CLK.outFreq" value="480 MHz" locked="false" accuracy=""/>
<clock_output id="USDHC1_CLK_ROOT.outFreq" value="176 MHz" locked="false" accuracy=""/>
<clock_output id="USDHC2_CLK_ROOT.outFreq" value="176 MHz" locked="false" accuracy=""/>
</clock_outputs>
<clock_settings>
<setting id="CCM.AHB_PODF.scale" value="1" locked="true"/>
<setting id="CCM.ARM_PODF.scale" value="1" locked="true"/>
<setting id="CCM.FLEXSPI_PODF.scale" value="4" locked="true"/>
<setting id="CCM.FLEXSPI_SEL.sel" value="CCM_ANALOG.PLL2_PFD2_CLK" locked="false"/>
<setting id="CCM.IPG_PODF.scale" value="4" locked="false"/>
<setting id="CCM.LPSPI_PODF.scale" value="5" locked="true"/>
<setting id="CCM.PERCLK_PODF.scale" value="2" locked="true"/>
<setting id="CCM.PRE_PERIPH_CLK_SEL.sel" value="CCM.ARM_PODF" locked="false"/>
<setting id="CCM.SEMC_PODF.scale" value="8" locked="false"/>
<setting id="CCM.TRACE_CLK_SEL.sel" value="CCM_ANALOG.PLL2_MAIN_CLK" locked="false"/>
<setting id="CCM.TRACE_PODF.scale" value="4" locked="true"/>
<setting id="CCM.USDHC1_PODF.scale" value="3" locked="true"/>
<setting id="CCM.USDHC2_PODF.scale" value="3" locked="true"/>
<setting id="CCM_ANALOG.PLL2.denom" value="1" locked="true"/>
<setting id="CCM_ANALOG.PLL2.num" value="0" locked="true"/>
<setting id="CCM_ANALOG.PLL2_BYPASS.sel" value="CCM_ANALOG.PLL2_OUT_CLK" locked="false"/>
<setting id="CCM_ANALOG.PLL2_PFD0_BYPASS.sel" value="CCM_ANALOG.PLL2_PFD0" locked="false"/>
<setting id="CCM_ANALOG.PLL2_PFD1_BYPASS.sel" value="CCM_ANALOG.PLL2_PFD1" locked="false"/>
<setting id="CCM_ANALOG.PLL2_PFD2_BYPASS.sel" value="CCM_ANALOG.PLL2_PFD2" locked="false"/>
<setting id="CCM_ANALOG.PLL2_PFD2_DIV.scale" value="18" locked="true"/>
<setting id="CCM_ANALOG.PLL2_PFD2_MUL.scale" value="18" locked="true"/>
<setting id="CCM_ANALOG.PLL2_PFD3_BYPASS.sel" value="CCM_ANALOG.PLL2_PFD3" locked="false"/>
<setting id="CCM_ANALOG.PLL2_PFD3_DIV.scale" value="18" locked="true"/>
<setting id="CCM_ANALOG.PLL2_PFD3_MUL.scale" value="18" locked="true"/>
<setting id="CCM_ANALOG.PLL3_BYPASS.sel" value="CCM_ANALOG.PLL3" locked="false"/>
<setting id="CCM_ANALOG.PLL3_PFD0_BYPASS.sel" value="CCM_ANALOG.PLL3_PFD0" locked="false"/>
<setting id="CCM_ANALOG.PLL3_PFD0_DIV.scale" value="22" locked="true"/>
<setting id="CCM_ANALOG.PLL3_PFD0_MUL.scale" value="18" locked="true"/>
<setting id="CCM_ANALOG.PLL3_PFD1_BYPASS.sel" value="CCM_ANALOG.PLL3_PFD1" locked="false"/>
<setting id="CCM_ANALOG.PLL3_PFD2_BYPASS.sel" value="CCM_ANALOG.PLL3_PFD2" locked="false"/>
<setting id="CCM_ANALOG.PLL3_PFD3_BYPASS.sel" value="CCM_ANALOG.PLL3_PFD3" locked="false"/>
<setting id="CCM_ANALOG.PLL3_PFD3_DIV.scale" value="18" locked="true"/>
<setting id="CCM_ANALOG.PLL3_PFD3_MUL.scale" value="18" locked="true"/>
<setting id="CCM_ANALOG.PLL4.denom" value="50" locked="false"/>
<setting id="CCM_ANALOG.PLL4.div" value="47" locked="false"/>
<setting id="CCM_ANALOG.PLL6_BYPASS.sel" value="CCM_ANALOG.PLL6" locked="false"/>
<setting id="CCM_ANALOG_PLL_ENET_ENABLE_CFG" value="Disabled" locked="false"/>
<setting id="CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_CFG" value="Disabled" locked="false"/>
<setting id="CCM_ANALOG_PLL_USB1_EN_USB_CLKS_CFG" value="Enabled" locked="false"/>
<setting id="CCM_ANALOG_PLL_USB1_EN_USB_CLKS_OUT_CFG" value="Enabled" locked="false"/>
<setting id="CCM_ANALOG_PLL_USB1_POWER_CFG" value="Yes" locked="false"/>
</clock_settings>
<called_from_default_init>true</called_from_default_init>
</clock_configuration>
</clock_configurations>
</clocks>
<dcdx name="DCDx" version="3.0" enabled="false" update_project_code="true">
<generated_project_files/>
<dcdx_profile>
<processor_version>13.0.2</processor_version>
<output_format>c_array</output_format>
</dcdx_profile>
<dcdx_configurations>
<dcdx_configuration name="Device_configuration">
<description></description>
<options/>
<command_groups/>
</dcdx_configuration>
</dcdx_configurations>
</dcdx>
<periphs name="Peripherals" version="12.0" enabled="false" update_project_code="true">
<generated_project_files/>
<peripherals_profile>
<processor_version>13.0.2</processor_version>
</peripherals_profile>
<functional_groups>
<functional_group name="BOARD_InitPeripherals" uuid="6d394465-bc9b-47f2-9a1f-3ca61f76d27b" called_from_default_init="true" id_prefix="" core="core0">
<description></description>
<options/>
<dependencies/>
<instances>
<instance name="NVIC" uuid="096e7e36-6917-481a-a4c5-06822cfc2da4" type="nvic" type_id="nvic_57b5eef3774cc60acaede6f5b8bddc67" mode="general" peripheral="NVIC" enabled="true" comment="" custom_name_enabled="false" editing_lock="false">
<config_set name="nvic">
<array name="interrupt_table"/>
<array name="interrupts"/>
</config_set>
</instance>
</instances>
</functional_group>
</functional_groups>
<components>
<component name="system" uuid="5dc935cc-5865-4d50-bac9-89ad440a12ee" type_id="system_54b53072540eeeb8f8e9343e71f28176">
<config_set_global name="global_system_definitions">
<setting name="user_definitions" value=""/>
<setting name="user_includes" value=""/>
</config_set_global>
</component>
<component name="msg" uuid="c2fe99b8-bf9b-437f-9446-a35000b06679" type_id="msg_6e2baaf3b97dbeef01c0043275f9a0e7">
<config_set_global name="global_messages"/>
</component>
<component name="generic_uart" uuid="eca93ea1-cadf-4247-bfdc-08769ef8ed12" type_id="generic_uart_8cae00565451cf2346eb1b8c624e73a6">
<config_set_global name="global_uart"/>
</component>
<component name="generic_can" uuid="fdf82c69-a73f-4f32-9699-457260453bc6" type_id="generic_can_1bfdd78b1af214566c1f23cf6a582d80">
<config_set_global name="global_can"/>
</component>
<component name="gpio_adapter_common" uuid="af80d7a8-d163-4a6f-839d-0ce2b15abffd" type_id="gpio_adapter_common_57579b9ac814fe26bf95df0a384c36b6">
<config_set_global name="global_gpio_adapter_common" quick_selection="default"/>
</component>
<component name="uart_cmsis_common" uuid="dca6ee55-a78d-4884-99bd-4f821b552213" type_id="uart_cmsis_common_9cb8e302497aa696fdbb5a4fd622c2a8">
<config_set_global name="global_USART_CMSIS_common" quick_selection="default"/>
</component>
<component name="generic_enet" uuid="4c34638b-b184-4e9d-8a81-5f3a1287180a" type_id="generic_enet_74db5c914f0ddbe47d86af40cb77a619">
<config_set_global name="global_enet"/>
</component>
</components>
</periphs>
<tee name="TEE" version="4.0" enabled="false" update_project_code="true">
<generated_project_files/>
<tee_profile>
<processor_version>N/A</processor_version>
</tee_profile>
</tee>
<common name="common" version="1.0" enabled="true" update_project_code="true">
<core name="core0" role="primary" project_name="Project"/>
</common>
</tools>
</configuration>