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# Copyright 2025 The JAX Authors. All Rights Reserved.
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#
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# Licensed under the Apache License, Version 2.0 (the "License");
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# you may not use this file except in compliance with the License.
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# You may obtain a copy of the License at
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#
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# http://www.apache.org/licenses/LICENSE-2.0
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#
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# Unless required by applicable law or agreed to in writing, software
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# distributed under the License is distributed on an "AS IS" BASIS,
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# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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# See the License for the specific language governing permissions and
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# limitations under the License.
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# ==============================================================================
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import itertools
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from jax.experimental.mosaic.gpu import fragmented_array as fa
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from jaxlib.mlir import ir
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from jaxlib.mlir.dialects import llvm
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from jaxlib.mlir.dialects import vector
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import numpy as np
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from . import utils
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SUPPORTED_F8_TYPES = (ir.Float8E4M3FNType, ir.Float8E5M2Type)
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class MMALayouts:
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"""Container for MMA layouts, providing a convenient way to create
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layouts for MMA operands based on warp configuration.
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"""
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def __init__(self, element_type: ir.Type):
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elems_per_reg = 32 // utils.bitwidth(element_type)
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k = 8 * elems_per_reg
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sub_k = 4 * elems_per_reg
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self.lhs = fa.TiledLayout(
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fa.Tiling(((64, k), (16, sub_k), (8, sub_k), (elems_per_reg,))),
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warp_dims=(-7,),
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lane_dims=(-3, -2),
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vector_dim=-1,
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)
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self.rhs = fa.TiledLayout(
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fa.Tiling(((8, k), (8, sub_k), (elems_per_reg,))),
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warp_dims=(fa.Replicated(4),),
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lane_dims=(-3, -2),
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vector_dim=-1,
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)
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self.acc = fa.TiledLayout(
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fa.Tiling(((64, 8), (16, 8), (8, 8), (2,))),
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warp_dims=(-7,),
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lane_dims=(-3, -2),
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vector_dim=-1,
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)
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def _ptx_dtype_str(dtype: ir.Type, *, is_signed: bool | None = None) -> str:
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if isinstance(dtype, ir.Float8E4M3FNType):
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return "e4m3"
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elif isinstance(dtype, ir.Float8E5M2Type):
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return "e5m2"
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elif isinstance(dtype, ir.IntegerType):
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if is_signed is None:
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raise ValueError("is_signed must be specified for integer types")
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prefix = "s" if is_signed else "u"
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return f"{prefix}{dtype.width}"
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return str(dtype)
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def _mma_single_tile(
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acc: fa.FragmentedArray, a: fa.FragmentedArray, b: fa.FragmentedArray
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) -> fa.FragmentedArray:
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"""Performs `acc + a @ b.T` using warp level MMA instructions."""
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i32 = ir.IntegerType.get_signless(32)
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k_tile = 256 // utils.bitwidth(a.mlir_dtype)
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assert a.shape == (64, k_tile)
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assert b.shape == (8, k_tile)
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assert acc.shape == (64, 8)
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assert a.mlir_dtype == b.mlir_dtype
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is_integer = isinstance(a.mlir_dtype, ir.IntegerType)
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assert acc.mlir_dtype == i32 if is_integer else ir.F32Type.get()
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assert acc.is_signed in {None, True}
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assert (
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isinstance(acc.layout, fa.TiledLayout)
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and isinstance(a.layout, fa.TiledLayout)
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and isinstance(b.layout, fa.TiledLayout)
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)
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num_acc_regs, num_a_regs, num_b_regs = 4, 4, 2
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acc_regs = [
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vector.extract(
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reg,
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dynamic_position=[],
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static_position=ir.DenseI64ArrayAttr.get([pos]),
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)
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for reg in acc.registers.flatten()
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for pos in range(acc.layout.vector_length)
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]
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a_regs = [utils.bitcast(r, i32) for r in a.registers.flatten()]
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b_regs = [utils.bitcast(r, i32) for r in b.registers.flatten()]
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# Make sure we have the right number of registers for the instruction.
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assert len(a_regs) == 4
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assert len(acc_regs) == 4
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assert len(b_regs) == 2
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a_ptx_dtype = _ptx_dtype_str(a.mlir_dtype, is_signed=a.is_signed)
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b_ptx_dtype = _ptx_dtype_str(b.mlir_dtype, is_signed=b.is_signed)
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acc_ptx_dtype = "s32" if is_integer else "f32"
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acc_constraint = "r" if is_integer else "f"
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instr = f"mma.sync.aligned.m16n8k{k_tile}.row.col.{acc_ptx_dtype}.{a_ptx_dtype}.{b_ptx_dtype}.{acc_ptx_dtype}"
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counter = itertools.count()
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n_regs_str = lambda n: (
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"{" + ",".join([f"${next(counter)}" for _ in range(n)]) + "}"
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)
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out_regs_str = n_regs_str(num_acc_regs)
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a_regs_str = n_regs_str(num_a_regs)
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b_regs_str = n_regs_str(num_b_regs)
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c_regs_str = n_regs_str(num_acc_regs)
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ptx = f"{instr} {out_regs_str}, {a_regs_str}, {b_regs_str}, {c_regs_str};"
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# See: https://llvm.org/docs/LangRef.html#inline-assembler-expressions
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constraints = (
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f"{','.join([f'={acc_constraint}']*num_acc_regs)},"
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f"{','.join(['r']*num_a_regs)},"
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f"{','.join(['r']*num_b_regs)},"
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f"{','.join([acc_constraint]*num_acc_regs)}"
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)
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in_operands = [*a_regs, *b_regs, *acc_regs]
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acc_struct_type = ir.Type.parse(
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f"!llvm.struct<({','.join(str(acc.mlir_dtype) for _ in acc_regs)})>"
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)
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out_regs_struct = llvm.inline_asm(
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acc_struct_type,
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in_operands,
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ptx,
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constraints,
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has_side_effects=False,
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)
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assert isinstance(out_regs_struct, ir.Value)
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out_regs = [
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llvm.extractvalue(acc.mlir_dtype, out_regs_struct, [i])
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for i in range(len(acc_regs))
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]
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vec_regs = []
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vec_undef = llvm.mlir_undef(ir.VectorType.get((2,), acc.mlir_dtype))
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for first, second in zip(out_regs[::2], out_regs[1::2]):
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vec = llvm.insertelement(vec_undef, first, position=utils.c(0, i32))
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vec = llvm.insertelement(vec, second, position=utils.c(1, i32))
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vec_regs.append(vec)
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out_regs = np.asarray(vec_regs, dtype=object).reshape(acc.registers.shape)
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return fa.FragmentedArray(
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_registers=out_regs, _layout=acc.layout, _is_signed=acc.is_signed
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)
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def mma(
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acc: fa.FragmentedArray,
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a: fa.FragmentedArray,
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b: fa.FragmentedArray,
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) -> fa.FragmentedArray:
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"""Computes `acc + a @ b.T` using synchronouse MMA instructions.
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All operands must have `TiledLayout`s. The layouts must be generated
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by the `MMALayouts` class, which ensures that the tiles are mapped
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to the warps correctly.
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Args:
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acc: A `FragmentedArray` with a `TiledLayout` generated from
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`MMALayouts.acc`.
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a: A `FragmentedArray` with a `TiledLayout` generated from
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`MMALayouts.lhs`.
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b: A `FragmentedArray` with a `TiledLayout` generated from `MMALayouts.rhs`.
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Returns:
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A new `FragmentedArray` with the result of the computation with
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the same type as `acc`.
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"""
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(m, k) = a.shape
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(n, k2) = b.shape
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(m2, n2) = acc.shape
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if m != m2:
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raise ValueError(f"M mismatch: {m} != {m2}")
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if n != n2:
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raise ValueError(f"N mismatch: {n} != {n2}")
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if k != k2:
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raise ValueError(f"K mismatch: {k} != {k2}")
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# todo(cperivol): A tile shape can have dimensions that are higher
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# multiples of the mma op size as long as those dimensions are not
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# sharded across warps.
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i4 = ir.IntegerType.get_signless(4)
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i8 = ir.IntegerType.get_signless(8)
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i32 = ir.IntegerType.get_signless(32)
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bf16 = ir.BF16Type.get()
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f16 = ir.F16Type.get()
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f8e4m3fn = ir.Float8E4M3FNType.get()
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f8e5m2 = ir.Float8E5M2Type.get()
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if (element_type := a.mlir_dtype) != b.mlir_dtype:
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raise ValueError(f"Dtype mismatch: {a.mlir_dtype} != {b.mlir_dtype}")
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if element_type not in (bf16, f16, f8e4m3fn, f8e5m2, i8, i4):
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raise NotImplementedError(f"Unsupported operand type: {element_type}")
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if isinstance(element_type, ir.IntegerType):
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if acc.mlir_dtype != i32:
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raise NotImplementedError("Only s32 accumulator supported for integer operands.")
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if not acc.is_signed:
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raise ValueError("Only signed accumulator supported for integer operands.")
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elif acc.mlir_dtype != ir.F32Type.get():
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raise NotImplementedError("Only f32 accumulator supported for floating operands.")
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layouts = MMALayouts(element_type)
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if layouts.lhs != a.layout:
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raise ValueError("Expected MMALayouts.lhs layout for A")
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if layouts.rhs != b.layout:
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raise ValueError("Expected MMALayouts.rhs layout for B")
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if layouts.acc != acc.layout:
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raise ValueError("Expected MMALayouts.acc layout for acc")
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assert isinstance(a.layout, fa.TiledLayout)
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assert isinstance(b.layout, fa.TiledLayout)
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assert isinstance(acc.layout, fa.TiledLayout)
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m_tile, k_tile = a.layout.base_tile_shape
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n_tile, k_tile2 = b.layout.base_tile_shape
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m_tile2, n_tile2 = acc.layout.base_tile_shape
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assert k_tile == k_tile2
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assert m_tile2 == m_tile
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assert n_tile2 == n_tile
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num_m_tiles, num_n_tiles, num_k_tiles = m // m_tile, n // n_tile, k // k_tile
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# Do not modify the accumualtor itself.
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acc = acc.copy()
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s = lambda idx, length: slice(idx * length, (idx + 1) * length)
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for k_idx in range(num_k_tiles):
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for m_idx in range(num_m_tiles):
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for n_idx in range(num_n_tiles):
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ms = s(m_idx, m_tile)
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ns = s(n_idx, n_tile)
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ks = s(k_idx, k_tile)
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acc[ms, ns] = _mma_single_tile(acc[ms, ns], a[ms, ks], b[ns, ks])
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return acc
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